Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2328	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2422	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2557	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2501	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2358	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2484	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2294	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2322	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2355	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2426	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2387	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2280	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2466	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2446	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2517	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2286	0	0
adc_en_ctl_rd_A	2147483647	2143	0	0
adc_fsm_rst_rd_A	2147483647	1992	0	0
adc_intr_ctl_rd_A	2147483647	2448	0	0
adc_lp_sample_ctl_rd_A	2147483647	2040	0	0
adc_pd_ctl_rd_A	2147483647	2102	0	0
adc_sample_ctl_rd_A	2147483647	2034	0	0
adc_wakeup_ctl_rd_A	2147483647	2100	0	0
intr_enable_rd_A	2147483647	2562	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2328	0	0
T11	116062	14	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	35	0	0
T17	0	24	0	0
T18	0	12	0	0
T19	0	37	0	0
T20	0	20	0	0
T21	0	18	0	0
T22	0	21	0	0
T23	0	25	0	0
T24	0	18	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2422	0	0
T11	116062	33	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	34	0	0
T17	0	37	0	0
T18	0	6	0	0
T19	0	25	0	0
T20	0	19	0	0
T21	0	22	0	0
T22	0	16	0	0
T23	0	36	0	0
T24	0	11	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2557	0	0
T11	116062	26	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	15	0	0
T17	0	37	0	0
T18	0	27	0	0
T19	0	21	0	0
T20	0	28	0	0
T21	0	22	0	0
T22	0	17	0	0
T23	0	43	0	0
T24	0	11	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2501	0	0
T11	116062	25	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	30	0	0
T17	0	23	0	0
T18	0	22	0	0
T19	0	42	0	0
T20	0	27	0	0
T21	0	14	0	0
T22	0	28	0	0
T23	0	23	0	0
T24	0	9	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2358	0	0
T11	116062	33	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	21	0	0
T17	0	31	0	0
T18	0	13	0	0
T19	0	27	0	0
T20	0	9	0	0
T21	0	6	0	0
T22	0	14	0	0
T23	0	31	0	0
T24	0	8	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2484	0	0
T11	116062	11	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	16	0	0
T17	0	20	0	0
T18	0	21	0	0
T19	0	31	0	0
T20	0	15	0	0
T21	0	40	0	0
T22	0	23	0	0
T23	0	29	0	0
T24	0	37	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2294	0	0
T11	116062	25	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	41	0	0
T17	0	28	0	0
T18	0	18	0	0
T19	0	29	0	0
T20	0	10	0	0
T21	0	23	0	0
T22	0	12	0	0
T23	0	25	0	0
T24	0	13	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2322	0	0
T11	116062	10	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	34	0	0
T17	0	34	0	0
T18	0	11	0	0
T19	0	36	0	0
T20	0	22	0	0
T21	0	4	0	0
T22	0	28	0	0
T23	0	45	0	0
T24	0	12	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2355	0	0
T11	116062	23	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	23	0	0
T17	0	26	0	0
T18	0	36	0	0
T19	0	21	0	0
T20	0	19	0	0
T21	0	19	0	0
T22	0	22	0	0
T23	0	34	0	0
T24	0	16	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2426	0	0
T11	116062	29	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	27	0	0
T17	0	42	0	0
T18	0	16	0	0
T19	0	41	0	0
T20	0	25	0	0
T21	0	22	0	0
T22	0	17	0	0
T23	0	48	0	0
T24	0	10	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2387	0	0
T11	116062	24	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	24	0	0
T17	0	53	0	0
T18	0	18	0	0
T19	0	21	0	0
T20	0	15	0	0
T21	0	40	0	0
T22	0	10	0	0
T23	0	41	0	0
T24	0	8	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2280	0	0
T11	116062	36	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	25	0	0
T17	0	54	0	0
T18	0	21	0	0
T19	0	26	0	0
T20	0	24	0	0
T21	0	25	0	0
T22	0	15	0	0
T23	0	41	0	0
T24	0	22	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2466	0	0
T11	116062	29	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	25	0	0
T17	0	41	0	0
T18	0	14	0	0
T19	0	33	0	0
T20	0	21	0	0
T21	0	17	0	0
T22	0	17	0	0
T23	0	30	0	0
T24	0	13	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2446	0	0
T11	116062	12	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	16	0	0
T17	0	41	0	0
T18	0	24	0	0
T19	0	28	0	0
T20	0	4	0	0
T21	0	26	0	0
T22	0	18	0	0
T23	0	28	0	0
T24	0	21	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2517	0	0
T11	116062	22	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	21	0	0
T17	0	43	0	0
T18	0	16	0	0
T19	0	19	0	0
T20	0	21	0	0
T21	0	24	0	0
T22	0	16	0	0
T23	0	35	0	0
T24	0	20	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2286	0	0
T11	116062	15	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	18	0	0
T17	0	51	0	0
T18	0	11	0	0
T19	0	13	0	0
T20	0	14	0	0
T21	0	22	0	0
T22	0	22	0	0
T23	0	31	0	0
T24	0	21	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2143	0	0
T11	116062	24	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	31	0	0
T17	0	35	0	0
T18	0	21	0	0
T19	0	18	0	0
T20	0	22	0	0
T21	0	29	0	0
T22	0	17	0	0
T23	0	39	0	0
T24	0	20	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1992	0	0
T11	116062	24	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	30	0	0
T17	0	31	0	0
T18	0	37	0	0
T19	0	31	0	0
T20	0	14	0	0
T21	0	16	0	0
T22	0	18	0	0
T23	0	36	0	0
T24	0	9	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2448	0	0
T11	116062	28	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	6	0	0
T17	0	20	0	0
T18	0	26	0	0
T19	0	16	0	0
T20	0	11	0	0
T21	0	45	0	0
T22	0	18	0	0
T23	0	36	0	0
T24	0	19	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2040	0	0
T11	116062	26	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	30	0	0
T17	0	45	0	0
T18	0	27	0	0
T19	0	29	0	0
T20	0	16	0	0
T21	0	12	0	0
T22	0	19	0	0
T23	0	36	0	0
T24	0	12	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2102	0	0
T11	116062	26	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	25	0	0
T17	0	20	0	0
T18	0	28	0	0
T19	0	30	0	0
T20	0	24	0	0
T21	0	20	0	0
T22	0	10	0	0
T23	0	42	0	0
T24	0	15	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2034	0	0
T11	116062	27	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	34	0	0
T17	0	42	0	0
T18	0	21	0	0
T19	0	36	0	0
T20	0	16	0	0
T21	0	12	0	0
T22	0	10	0	0
T23	0	41	0	0
T24	0	17	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2100	0	0
T11	116062	9	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	36	0	0
T17	0	40	0	0
T18	0	18	0	0
T19	0	26	0	0
T20	0	16	0	0
T21	0	33	0	0
T22	0	17	0	0
T23	0	24	0	0
T24	0	9	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2562	0	0
T11	116062	28	0	0
T12	811971	0	0	0
T13	626429	0	0	0
T14	552605	0	0	0
T16	0	47	0	0
T17	0	80	0	0
T18	0	12	0	0
T19	0	39	0	0
T20	0	38	0	0
T21	0	15	0	0
T22	0	27	0	0
T25	129037	0	0	0
T26	48747	0	0	0
T27	334917	0	0	0
T28	150242	0	0	0
T29	72207	0	0	0
T30	359662	0	0	0
T31	0	4	0	0
T32	0	10	0	0