Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1215253	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1188486

1

T1

465

T2

30

T3

1352

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2107065	1			T1	861		T3	1877		T4	4020
values[0x0]	148135	1			T1	45		T2	35		T3	356
values[0x1]	148539	1			T1	55		T2	26		T3	353

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	973712	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1430027

1

T1

564

T2

32

T3

1599

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10133	1			T1	2		T3	9		T4	14
valid_sources[0x01]	8954	1			T1	15		T3	16		T4	20
valid_sources[0x02]	11595	1			T1	4		T3	6		T4	17
valid_sources[0x03]	6807	1			T1	4		T3	2		T4	16
valid_sources[0x04]	24338	1			T1	2		T3	4		T4	28
valid_sources[0x05]	7485	1			T1	1		T2	4		T3	3
valid_sources[0x06]	8457	1			T1	1		T3	5		T4	11
valid_sources[0x07]	16179	1			T1	3		T2	1		T3	8
valid_sources[0x08]	7265	1			T3	26		T4	25		T5	43
valid_sources[0x09]	7296	1			T1	6		T4	16		T5	18
valid_sources[0x0a]	10821	1			T4	9		T5	27		T6	19
valid_sources[0x0b]	12945	1			T3	11		T4	21		T5	91
valid_sources[0x0c]	8782	1			T1	5		T3	2		T4	20
valid_sources[0x0d]	7521	1			T3	28		T4	21		T5	9
valid_sources[0x0e]	7645	1			T1	2		T2	1		T4	21
valid_sources[0x0f]	7231	1			T1	3		T3	5		T4	16
valid_sources[0x10]	7568	1			T1	9		T3	4		T4	15
valid_sources[0x11]	7377	1			T1	5		T3	23		T4	16
valid_sources[0x12]	9517	1			T1	3		T2	1		T3	20
valid_sources[0x13]	11431	1			T1	2		T3	4		T4	17
valid_sources[0x14]	13667	1			T1	2		T3	9		T4	12
valid_sources[0x15]	7202	1			T1	5		T3	10		T4	23
valid_sources[0x16]	7553	1			T1	7		T3	18		T4	14
valid_sources[0x17]	7183	1			T1	5		T3	7		T4	23
valid_sources[0x18]	9039	1			T1	5		T3	8		T4	13
valid_sources[0x19]	8188	1			T3	16		T4	21		T5	16
valid_sources[0x1a]	9513	1			T1	1		T3	18		T4	19
valid_sources[0x1b]	7787	1			T1	5		T3	6		T4	19
valid_sources[0x1c]	11217	1			T1	4		T2	1		T3	17
valid_sources[0x1d]	7512	1			T4	17		T5	105		T6	13
valid_sources[0x1e]	10193	1			T1	6		T3	14		T4	29
valid_sources[0x1f]	7030	1			T1	3		T3	8		T4	12
valid_sources[0x20]	7141	1			T1	14		T3	7		T4	25
valid_sources[0x21]	6797	1			T1	1		T3	6		T4	14
valid_sources[0x22]	8000	1			T1	1		T2	1		T3	17
valid_sources[0x23]	19626	1			T1	5		T3	1		T4	14
valid_sources[0x24]	11489	1			T1	1		T2	1		T3	23
valid_sources[0x25]	10049	1			T1	3		T3	8		T4	16
valid_sources[0x26]	10679	1			T1	1		T2	1		T3	14
valid_sources[0x27]	8310	1			T1	2		T3	14		T4	18
valid_sources[0x28]	11297	1			T1	4		T3	15		T4	14
valid_sources[0x29]	7002	1			T1	1		T2	2		T3	3
valid_sources[0x2a]	7936	1			T1	5		T3	2		T4	19
valid_sources[0x2b]	6951	1			T1	1		T3	20		T4	17
valid_sources[0x2c]	7731	1			T1	7		T4	17		T5	51
valid_sources[0x2d]	11272	1			T3	8		T4	22		T5	62
valid_sources[0x2e]	10385	1			T1	1		T4	4		T5	36
valid_sources[0x2f]	6933	1			T4	9		T5	60		T6	22
valid_sources[0x30]	6909	1			T1	1		T3	9		T4	13
valid_sources[0x31]	7542	1			T1	4		T3	5		T4	25
valid_sources[0x32]	7175	1			T4	19		T5	86		T6	19
valid_sources[0x33]	7929	1			T3	5		T4	21		T5	18
valid_sources[0x34]	10479	1			T1	3		T2	1		T3	13
valid_sources[0x35]	7914	1			T1	2		T2	1		T3	7
valid_sources[0x36]	7547	1			T1	11		T3	9		T4	11
valid_sources[0x37]	7185	1			T1	3		T3	12		T4	22
valid_sources[0x38]	11145	1			T1	1		T3	6		T4	24
valid_sources[0x39]	7002	1			T1	1		T3	6		T4	13
valid_sources[0x3a]	20294	1			T3	16		T4	11		T5	15
valid_sources[0x3b]	7025	1			T1	5		T3	10		T4	16
valid_sources[0x3c]	7037	1			T1	2		T3	21		T4	21
valid_sources[0x3d]	11301	1			T1	2		T2	1		T3	9
valid_sources[0x3e]	7007	1			T3	5		T4	14		T5	42
valid_sources[0x3f]	12767	1			T1	4		T3	5		T4	18
valid_sources[0x40]	7222	1			T1	1		T3	11		T4	14
valid_sources[0x41]	7531	1			T1	2		T2	1		T3	1
valid_sources[0x42]	14236	1			T1	4		T2	1		T3	8
valid_sources[0x43]	7904	1			T1	13		T3	26		T4	19
valid_sources[0x44]	9129	1			T1	2		T3	5		T4	16
valid_sources[0x45]	6843	1			T1	2		T2	1		T3	6
valid_sources[0x46]	6974	1			T1	4		T2	1		T3	13
valid_sources[0x47]	7464	1			T1	12		T3	9		T4	25
valid_sources[0x48]	9921	1			T1	2		T3	8		T4	17
valid_sources[0x49]	7365	1			T1	5		T3	18		T4	19
valid_sources[0x4a]	6881	1			T1	10		T3	11		T4	17
valid_sources[0x4b]	11375	1			T1	4		T3	13		T4	10
valid_sources[0x4c]	11533	1			T1	8		T2	1		T3	9
valid_sources[0x4d]	11789	1			T1	5		T3	12		T4	9
valid_sources[0x4e]	7528	1			T1	1		T3	12		T4	17
valid_sources[0x4f]	11682	1			T1	10		T3	12		T4	24
valid_sources[0x50]	7548	1			T1	13		T3	212		T4	10
valid_sources[0x51]	24242	1			T1	2		T3	3		T4	15
valid_sources[0x52]	10489	1			T1	3		T3	7		T4	12
valid_sources[0x53]	11657	1			T1	5		T3	11		T4	17
valid_sources[0x54]	11071	1			T3	1		T4	15		T5	22
valid_sources[0x55]	6978	1			T1	6		T3	10		T4	12
valid_sources[0x56]	7119	1			T2	1		T3	8		T4	22
valid_sources[0x57]	11424	1			T1	5		T2	1		T3	5
valid_sources[0x58]	7686	1			T1	11		T2	1		T3	9
valid_sources[0x59]	16420	1			T1	5		T3	8		T4	18
valid_sources[0x5a]	8288	1			T1	8		T3	4		T4	16
valid_sources[0x5b]	7339	1			T1	2		T3	2		T4	15
valid_sources[0x5c]	7270	1			T1	1		T3	4		T4	16
valid_sources[0x5d]	7222	1			T1	2		T3	5		T4	11
valid_sources[0x5e]	8206	1			T1	1		T3	3		T4	17
valid_sources[0x5f]	6992	1			T1	2		T3	11		T4	10
valid_sources[0x60]	6999	1			T1	2		T2	1		T3	8
valid_sources[0x61]	17934	1			T1	3		T4	14		T5	16
valid_sources[0x62]	8798	1			T1	8		T3	10		T4	22
valid_sources[0x63]	7568	1			T1	1		T3	1		T4	14
valid_sources[0x64]	6920	1			T1	1		T2	1		T3	6
valid_sources[0x65]	16020	1			T1	6		T3	10		T4	23
valid_sources[0x66]	7546	1			T1	3		T2	2		T3	2
valid_sources[0x67]	7614	1			T1	2		T3	5		T4	26
valid_sources[0x68]	7151	1			T1	12		T3	2		T4	11
valid_sources[0x69]	8037	1			T1	3		T3	5		T4	12
valid_sources[0x6a]	7219	1			T1	6		T3	6		T4	16
valid_sources[0x6b]	7027	1			T1	1		T3	5		T4	20
valid_sources[0x6c]	10470	1			T1	2		T3	7		T4	13
valid_sources[0x6d]	6750	1			T1	2		T3	11		T4	13
valid_sources[0x6e]	11624	1			T1	7		T3	20		T4	18
valid_sources[0x6f]	7168	1			T1	11		T3	12		T4	25
valid_sources[0x70]	12218	1			T1	7		T3	5		T4	11
valid_sources[0x71]	6954	1			T1	1		T4	14		T5	25
valid_sources[0x72]	7535	1			T1	1		T3	29		T4	21
valid_sources[0x73]	7629	1			T1	6		T3	2		T4	10
valid_sources[0x74]	8212	1			T1	18		T3	19		T4	18
valid_sources[0x75]	7078	1			T3	8		T4	21		T5	26
valid_sources[0x76]	15315	1			T1	11		T2	1		T3	9
valid_sources[0x77]	6955	1			T1	3		T3	3		T4	14
valid_sources[0x78]	12372	1			T1	3		T3	14		T4	27
valid_sources[0x79]	11786	1			T1	1		T3	9		T4	6
valid_sources[0x7a]	12455	1			T1	5		T3	5		T4	21
valid_sources[0x7b]	7091	1			T1	1		T3	15		T4	23
valid_sources[0x7c]	6538	1			T3	22		T4	23		T5	5
valid_sources[0x7d]	7362	1			T1	1		T3	5		T4	17
valid_sources[0x7e]	7084	1			T1	2		T3	7		T4	16
valid_sources[0x7f]	6705	1			T1	3		T4	18		T5	38
valid_sources[0x80]	11169	1			T1	1		T3	15		T4	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1050621

1

T1

418

T3

986

T4

1984

values[0x0]

all_enables

biggest_size

80508

1

T1

27

T2

19

T3

199

values[0x1]

all_enables

biggest_size

57357

1

T1

20

T2

11

T3

167