Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29081	1			T1	8		T3	50		T4	6
auto[PWRUP]	106	1			T5	1		T35	1		T36	5
auto[ONEST_0]	73	1			T5	4		T10	1		T35	2
auto[ONEST_021]	16	1			T12	1		T207	1		T208	1
auto[ONEST_1]	66	1			T5	1		T10	1		T35	1
auto[ONEST_DONE]	6	1			T36	1		T12	1		T155	1
auto[LP_0]	133	1			T5	2		T10	3		T35	1
auto[LP_021]	28	1			T36	2		T209	1		T96	1
auto[LP_1]	137	1			T5	2		T10	2		T35	4
auto[LP_EVAL]	78	1			T3	2		T5	5		T10	1
auto[LP_SLP]	510	1			T5	6		T10	1		T35	13
auto[LP_PWRUP]	31	1			T35	1		T36	2		T210	1
auto[NP_0]	153	1			T3	1		T5	1		T10	2
auto[NP_021]	40	1			T35	1		T36	3		T77	1
auto[NP_1]	157	1			T3	1		T5	1		T35	4
auto[NP_EVAL]	49	1			T5	1		T10	1		T36	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T210

1

T155

1

T211

3

min

28569

1

T1

8

T3

47

T4

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28576	1			T1	8		T3	47		T4	6
pow[0x1]	6	1			T36	1		T212	2		T213	1
pow[0x2]	19	1			T35	1		T77	1		T214	1
pow[0x3]	31	1			T5	3		T36	1		T214	1
pow[0x4]	68	1			T3	1		T10	1		T35	1
pow[0x5]	133	1			T5	1		T10	1		T35	4
pow[0x6]	239	1			T3	1		T5	5		T35	2
pow[0x7]	565	1			T3	3		T5	9		T10	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

176

1

T5

4

T10

2

T35

1

min

28080

1

T1

8

T3

47

T4

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28080	1			T1	8		T3	47		T4	6
pow[0x3]	1	1			T10	1		-	-		-	-
pow[0x7]	6	1			T3	1		T10	1		T37	1
pow[0x8]	6	1			T215	2		T216	1		T217	1
pow[0x9]	15	1			T36	1		T77	1		T93	1
pow[0xa]	22	1			T10	1		T37	1		T13	1
pow[0xb]	30	1			T5	1		T35	1		T36	1
pow[0xc]	85	1			T35	1		T36	9		T77	1
pow[0xd]	155	1			T5	5		T35	5		T36	6
pow[0xe]	288	1			T3	1		T5	5		T10	2
pow[0xf]	575	1			T5	11		T10	4		T35	7