Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2380	1			T3	16		T5	27		T6	2
auto[PWRUP]	111	1			T3	1		T5	2		T10	1
auto[ONEST_0]	80	1			T5	1		T35	2		T36	1
auto[ONEST_021]	26	1			T36	1		T37	1		T27	1
auto[ONEST_1]	82	1			T5	1		T10	3		T35	2
auto[ONEST_DONE]	1	1			T346	1		-	-		-	-
auto[LP_0]	122	1			T5	1		T10	2		T35	1
auto[LP_021]	34	1			T3	1		T35	2		T77	1
auto[LP_1]	152	1			T5	4		T10	1		T35	1
auto[LP_EVAL]	71	1			T3	1		T5	1		T10	1
auto[LP_SLP]	502	1			T3	1		T5	5		T10	1
auto[LP_PWRUP]	27	1			T5	2		T10	1		T36	1
auto[NP_0]	218	1			T5	3		T10	1		T35	1
auto[NP_021]	50	1			T10	1		T35	1		T36	3
auto[NP_1]	230	1			T3	4		T5	1		T36	4
auto[NP_EVAL]	35	1			T3	1		T5	1		T37	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T35

1

T290

1

T347

1

min

1968

1

T3

22

T5

13

T6

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1984	1			T3	22		T5	14		T6	2
pow[0x1]	9	1			T36	1		T12	1		T210	1
pow[0x2]	26	1			T36	1		T77	1		T37	1
pow[0x3]	27	1			T5	1		T35	1		T36	1
pow[0x4]	75	1			T5	1		T35	1		T36	5
pow[0x5]	129	1			T5	2		T10	1		T35	1
pow[0x6]	290	1			T5	3		T10	3		T35	2
pow[0x7]	510	1			T5	10		T10	4		T35	12

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

206

1

T3

1

T5

3

T10

2

min

1407

1

T3

19

T5

7

T6

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1413	1			T3	19		T5	7		T6	2
pow[0x1]	14	1			T3	1		T25	1		T14	1
pow[0x2]	26	1			T13	1		T30	2		T31	2
pow[0x3]	35	1			T26	1		T27	2		T13	1
pow[0x4]	56	1			T3	2		T25	1		T27	4
pow[0x6]	2	1			T208	1		T348	1		-	-
pow[0x7]	3	1			T215	1		T213	1		T348	1
pow[0x8]	3	1			T349	1		T347	1		T213	1
pow[0x9]	6	1			T210	1		T93	1		T350	1
pow[0xa]	14	1			T35	1		T36	2		T207	1
pow[0xb]	41	1			T35	1		T37	1		T214	1
pow[0xc]	83	1			T5	3		T10	1		T35	2
pow[0xd]	170	1			T3	1		T5	5		T10	6
pow[0xe]	281	1			T5	5		T10	1		T35	4
pow[0xf]	582	1			T3	1		T5	10		T10	1