Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T10

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T6,T7
1	0	Covered	T3,T4,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T3,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T11
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T11
0	1	Covered	T5,T6,T11
1	0	Covered	T5,T6,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T5,T6,T7
1	0	Covered	T3,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T6,T7
1	0	Covered	T3,T4,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T4,T6,T21
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T21
0	1	Covered	T4,T6,T21
1	0	Covered	T4,T6,T21

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T6,T7
1	0	Covered	T3,T4,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T3,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T11
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T11
0	1	Covered	T5,T6,T11
1	0	Covered	T5,T6,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T5,T6,T7
1	0	Covered	T3,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T6,T7
1	0	Covered	T3,T4,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T5,T6
1	1	1	Covered	T1,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T4,T6
1	1	1	Covered	T1,T4,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T5,T6
1	1	1	Covered	T1,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T1,T3,T6
1	1	1	Covered	T1,T3,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T5

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T11
1	0	Covered	T1,T3,T4

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T8,T9,T76
1	1	Covered	T1,T8,T11

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T10
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T21

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	34210313	33893329	0	0
gen_filter_match[0].MatchCheck00_A	34210313	10376629	0	0
gen_filter_match[0].MatchCheck01_A	34210313	2464735	0	0
gen_filter_match[0].MatchCheck10_A	34210313	2514122	0	0
gen_filter_match[0].MatchCheck11_A	34210313	18537843	0	0
gen_filter_match[1].MatchCheck00_A	34210313	10625585	0	0
gen_filter_match[1].MatchCheck01_A	34210313	1024937	0	0
gen_filter_match[1].MatchCheck10_A	34210313	1454004	0	0
gen_filter_match[1].MatchCheck11_A	34210313	20788803	0	0
gen_filter_match[2].MatchCheck00_A	34210313	11538664	0	0
gen_filter_match[2].MatchCheck01_A	34210313	473088	0	0
gen_filter_match[2].MatchCheck10_A	34210313	611697	0	0
gen_filter_match[2].MatchCheck11_A	34210313	21269880	0	0
gen_filter_match[3].MatchCheck00_A	34210313	13143172	0	0
gen_filter_match[3].MatchCheck01_A	34210313	366180	0	0
gen_filter_match[3].MatchCheck10_A	34210313	363497	0	0
gen_filter_match[3].MatchCheck11_A	34210313	20020480	0	0
gen_filter_match[4].MatchCheck00_A	34210313	12030378	0	0
gen_filter_match[4].MatchCheck01_A	34210313	10	0	0
gen_filter_match[4].MatchCheck10_A	34210313	103	0	0
gen_filter_match[4].MatchCheck11_A	34210313	21862838	0	0
gen_filter_match[5].MatchCheck00_A	34210313	12652651	0	0
gen_filter_match[5].MatchCheck01_A	34210313	35218	0	0
gen_filter_match[5].MatchCheck10_A	34210313	65088	0	0
gen_filter_match[5].MatchCheck11_A	34210313	21140372	0	0
gen_filter_match[6].MatchCheck00_A	34210313	12098671	0	0
gen_filter_match[6].MatchCheck01_A	34210313	82511	0	0
gen_filter_match[6].MatchCheck10_A	34210313	41465	0	0
gen_filter_match[6].MatchCheck11_A	34210313	21670682	0	0
gen_filter_match[7].MatchCheck00_A	34210313	12696611	0	0
gen_filter_match[7].MatchCheck01_A	34210313	163544	0	0
gen_filter_match[7].MatchCheck10_A	34210313	88526	0	0
gen_filter_match[7].MatchCheck11_A	34210313	20944648	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	33893329	0	0
T1	41425	41358	0	0
T2	9356	9297	0	0
T3	39418	37966	0	0
T4	32435	32362	0	0
T5	93099	89294	0	0
T6	65514	65310	0	0
T7	65680	65586	0	0
T8	120068	119973	0	0
T9	36929	36876	0	0
T10	12737	10896	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	10376629	0	0
T1	41425	4	0	0
T2	9356	9297	0	0
T3	39418	19399	0	0
T4	32435	3	0	0
T5	93099	53921	0	0
T6	65514	7	0	0
T7	65680	3	0	0
T8	120068	4	0	0
T9	36929	4	0	0
T10	12737	10375	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	2464735	0	0
T6	65514	32647	0	0
T7	65680	0	0	0
T8	120068	0	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T11	72016	0	0	0
T12	0	18458	0	0
T21	35697	0	0	0
T32	39339	0	0	0
T35	25951	0	0	0
T36	106732	0	0	0
T76	0	38197	0	0
T91	0	32313	0	0
T122	0	32401	0	0
T123	0	33382	0	0
T124	0	34510	0	0
T125	0	33054	0	0
T126	0	32112	0	0
T127	0	33408	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	2514122	0	0
T1	41425	1	0	0
T2	9356	0	0	0
T3	39418	154	0	0
T4	32435	32359	0	0
T5	93099	3	0	0
T6	65514	0	0	0
T7	65680	32642	0	0
T8	120068	0	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T33	0	33759	0	0
T41	0	33100	0	0
T128	0	32731	0	0
T129	0	32781	0	0
T130	0	38766	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	18537843	0	0
T1	41425	41353	0	0
T2	9356	0	0	0
T3	39418	18413	0	0
T4	32435	0	0	0
T5	93099	35370	0	0
T6	65514	32656	0	0
T7	65680	32941	0	0
T8	120068	119969	0	0
T9	36929	36872	0	0
T10	12737	521	0	0
T11	0	39468	0	0
T35	0	331	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	10625585	0	0
T1	41425	4	0	0
T2	9356	9297	0	0
T3	39418	37966	0	0
T4	32435	3	0	0
T5	93099	24013	0	0
T6	65514	7	0	0
T7	65680	65586	0	0
T8	120068	4	0	0
T9	36929	4	0	0
T10	12737	10896	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	1024937	0	0
T5	93099	31156	0	0
T6	65514	0	0	0
T7	65680	0	0	0
T8	120068	0	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T11	72016	0	0	0
T21	35697	0	0	0
T28	0	2231	0	0
T32	39339	0	0	0
T35	25951	0	0	0
T36	0	33279	0	0
T131	0	32448	0	0
T132	0	32383	0	0
T133	0	33182	0	0
T134	0	31712	0	0
T135	0	32730	0	0
T136	0	33079	0	0
T137	0	38796	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	1454004	0	0
T1	41425	1	0	0
T2	9356	0	0	0
T3	39418	0	0	0
T4	32435	0	0	0
T5	93099	34125	0	0
T6	65514	0	0	0
T7	65680	0	0	0
T8	120068	0	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T11	0	32466	0	0
T27	0	7582	0	0
T31	0	19137	0	0
T32	0	39235	0	0
T33	0	34074	0	0
T133	0	33130	0	0
T138	0	32858	0	0
T139	0	32762	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	20788803	0	0
T1	41425	41353	0	0
T2	9356	0	0	0
T3	39418	0	0	0
T4	32435	32359	0	0
T5	93099	0	0	0
T6	65514	65303	0	0
T7	65680	0	0	0
T8	120068	119969	0	0
T9	36929	36872	0	0
T10	12737	0	0	0
T21	0	35604	0	0
T33	0	32599	0	0
T34	0	34099	0	0
T74	0	33073	0	0
T76	0	81480	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	11538664	0	0
T1	41425	4	0	0
T2	9356	9297	0	0
T3	39418	20862	0	0
T4	32435	3	0	0
T5	93099	24012	0	0
T6	65514	32663	0	0
T7	65680	3	0	0
T8	120068	4	0	0
T9	36929	4	0	0
T10	12737	10896	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	473088	0	0
T14	110090	20106	0	0
T140	104518	33383	0	0
T141	0	32794	0	0
T142	0	39518	0	0
T143	0	33018	0	0
T144	0	32907	0	0
T145	0	33135	0	0
T146	0	21453	0	0
T147	0	32935	0	0
T148	0	2	0	0
T149	65876	0	0	0
T150	1203	0	0	0
T151	623	0	0	0
T152	97183	0	0	0
T153	24997	0	0	0
T154	67119	0	0	0
T155	34527	0	0	0
T156	37035	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	611697	0	0
T1	41425	1	0	0
T2	9356	0	0	0
T3	39418	2	0	0
T4	32435	0	0	0
T5	93099	5	0	0
T6	65514	0	0	0
T7	65680	0	0	0
T8	120068	0	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T30	0	14173	0	0
T31	0	11664	0	0
T157	0	33344	0	0
T158	0	32107	0	0
T159	0	1	0	0
T160	0	2	0	0
T161	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	21269880	0	0
T1	41425	41353	0	0
T2	9356	0	0	0
T3	39418	17102	0	0
T4	32435	32359	0	0
T5	93099	65277	0	0
T6	65514	32647	0	0
T7	65680	65583	0	0
T8	120068	119969	0	0
T9	36929	36872	0	0
T10	12737	0	0	0
T11	0	32466	0	0
T21	0	35604	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	13143172	0	0
T1	41425	4	0	0
T2	9356	9297	0	0
T3	39418	37812	0	0
T4	32435	3	0	0
T5	93099	89294	0	0
T6	65514	32654	0	0
T7	65680	32645	0	0
T8	120068	4	0	0
T9	36929	36876	0	0
T10	12737	10896	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	366180	0	0
T136	67915	0	0	0
T160	110059	1	0	0
T161	39125	0	0	0
T162	0	33604	0	0
T163	0	33033	0	0
T164	0	40576	0	0
T165	0	51265	0	0
T166	0	33795	0	0
T167	0	31981	0	0
T168	0	34424	0	0
T169	0	32463	0	0
T170	0	1	0	0
T171	68	0	0	0
T172	39302	0	0	0
T173	87	0	0	0
T174	8204	0	0	0
T175	57	0	0	0
T176	1006	0	0	0
T177	1026	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	363497	0	0
T1	41425	1	0	0
T2	9356	0	0	0
T3	39418	1	0	0
T4	32435	0	0	0
T5	93099	0	0	0
T6	65514	0	0	0
T7	65680	1	0	0
T8	120068	0	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T14	0	16	0	0
T22	0	32400	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	20020480	0	0
T1	41425	41353	0	0
T2	9356	0	0	0
T3	39418	153	0	0
T4	32435	32359	0	0
T5	93099	0	0	0
T6	65514	32656	0	0
T7	65680	32940	0	0
T8	120068	119969	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T11	0	32466	0	0
T21	0	35604	0	0
T32	0	39235	0	0
T36	0	33279	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	12030378	0	0
T1	41425	4	0	0
T2	9356	9297	0	0
T3	39418	21016	0	0
T4	32435	32362	0	0
T5	93099	55171	0	0
T6	65514	7	0	0
T7	65680	65586	0	0
T8	120068	4	0	0
T9	36929	4	0	0
T10	12737	10896	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	10	0	0
T148	0	2	0	0
T179	115178	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	2	0	0
T186	33010	0	0	0
T187	80806	0	0	0
T188	123148	0	0	0
T189	33557	0	0	0
T190	1166	0	0	0
T191	805	0	0	0
T192	121164	0	0	0
T193	95	0	0	0
T194	1239	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	103	0	0
T1	41425	1	0	0
T2	9356	0	0	0
T3	39418	3	0	0
T4	32435	0	0	0
T5	93099	2	0	0
T6	65514	0	0	0
T7	65680	0	0	0
T8	120068	0	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T14	0	17	0	0
T131	0	1	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	2	0	0
T178	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	21862838	0	0
T1	41425	41353	0	0
T2	9356	0	0	0
T3	39418	16947	0	0
T4	32435	0	0	0
T5	93099	34121	0	0
T6	65514	65303	0	0
T7	65680	0	0	0
T8	120068	119969	0	0
T9	36929	36872	0	0
T10	12737	0	0	0
T11	0	39468	0	0
T21	0	35604	0	0
T32	0	39235	0	0
T36	0	33279	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	12652651	0	0
T1	41425	5	0	0
T2	9356	9297	0	0
T3	39418	21016	0	0
T4	32435	32362	0	0
T5	93099	89294	0	0
T6	65514	32663	0	0
T7	65680	3	0	0
T8	120068	4	0	0
T9	36929	36876	0	0
T10	12737	10896	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	35218	0	0
T148	0	2	0	0
T167	0	1	0	0
T170	0	2	0	0
T179	115178	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T186	33010	0	0	0
T187	80806	0	0	0
T188	123148	0	0	0
T189	33557	0	0	0
T190	1166	0	0	0
T191	805	0	0	0
T192	121164	0	0	0
T193	95	0	0	0
T194	1239	0	0	0
T195	0	35205	0	0
T196	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	65088	0	0
T1	41425	1	0	0
T2	9356	0	0	0
T3	39418	4	0	0
T4	32435	0	0	0
T5	93099	0	0	0
T6	65514	0	0	0
T7	65680	1	0	0
T8	120068	0	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T12	0	3	0	0
T13	0	2	0	0
T34	0	1	0	0
T131	0	1	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	21140372	0	0
T1	41425	41352	0	0
T2	9356	0	0	0
T3	39418	16946	0	0
T4	32435	0	0	0
T5	93099	0	0	0
T6	65514	32647	0	0
T7	65680	65582	0	0
T8	120068	119969	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T11	0	32466	0	0
T32	0	39235	0	0
T33	0	66358	0	0
T34	0	34098	0	0
T74	0	33073	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	12098671	0	0
T1	41425	5	0	0
T2	9356	9297	0	0
T3	39418	21016	0	0
T4	32435	3	0	0
T5	93099	55171	0	0
T6	65514	65310	0	0
T7	65680	3	0	0
T8	120068	4	0	0
T9	36929	4	0	0
T10	12737	10896	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	82511	0	0
T26	14428	7711	0	0
T37	26416	0	0	0
T41	65900	0	0	0
T56	102	0	0	0
T99	1216	0	0	0
T122	98579	0	0	0
T129	65341	0	0	0
T131	65633	0	0	0
T138	65558	0	0	0
T148	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T184	0	1	0	0
T197	0	1	0	0
T199	0	36516	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	0	38270	0	0
T203	33464	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	41465	0	0
T1	41425	1	0	0
T2	9356	0	0	0
T3	39418	4	0	0
T4	32435	0	0	0
T5	93099	3	0	0
T6	65514	0	0	0
T7	65680	1	0	0
T8	120068	0	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T12	0	3	0	0
T13	0	3	0	0
T93	0	1	0	0
T131	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	21670682	0	0
T1	41425	41352	0	0
T2	9356	0	0	0
T3	39418	16946	0	0
T4	32435	32359	0	0
T5	93099	34120	0	0
T6	65514	0	0	0
T7	65680	65582	0	0
T8	120068	119969	0	0
T9	36929	36872	0	0
T10	12737	0	0	0
T11	0	71934	0	0
T33	0	34074	0	0
T36	0	33279	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	12696611	0	0
T1	41425	5	0	0
T2	9356	9297	0	0
T3	39418	37966	0	0
T4	32435	3	0	0
T5	93099	55172	0	0
T6	65514	65310	0	0
T7	65680	4	0	0
T8	120068	4	0	0
T9	36929	36876	0	0
T10	12737	10896	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	163544	0	0
T7	65680	32940	0	0
T8	120068	0	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T11	72016	0	0	0
T21	35697	0	0	0
T32	39339	0	0	0
T35	25951	0	0	0
T36	106732	0	0	0
T49	1635	0	0	0
T131	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T184	0	1	0	0
T198	0	1	0	0
T199	0	33167	0	0
T201	0	1	0	0
T204	0	1	0	0
T205	0	32598	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	88526	0	0
T1	41425	1	0	0
T2	9356	0	0	0
T3	39418	0	0	0
T4	32435	0	0	0
T5	93099	2	0	0
T6	65514	0	0	0
T7	65680	0	0	0
T8	120068	0	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T12	0	3	0	0
T34	0	1	0	0
T93	0	1	0	0
T131	0	1	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T206	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34210313	20944648	0	0
T1	41425	41352	0	0
T2	9356	0	0	0
T3	39418	0	0	0
T4	32435	32359	0	0
T5	93099	34120	0	0
T6	65514	0	0	0
T7	65680	32642	0	0
T8	120068	119969	0	0
T9	36929	0	0	0
T10	12737	0	0	0
T11	0	39468	0	0
T21	0	35604	0	0
T32	0	39235	0	0
T33	0	32599	0	0
T36	0	33279	0	0