Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2446	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2389	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2412	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2383	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2430	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2373	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2159	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2420	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2398	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2177	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2438	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2594	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2521	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2223	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2465	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2384	0	0
adc_en_ctl_rd_A	2147483647	1915	0	0
adc_fsm_rst_rd_A	2147483647	1662	0	0
adc_intr_ctl_rd_A	2147483647	2140	0	0
adc_lp_sample_ctl_rd_A	2147483647	1775	0	0
adc_pd_ctl_rd_A	2147483647	2061	0	0
adc_sample_ctl_rd_A	2147483647	1717	0	0
adc_wakeup_ctl_rd_A	2147483647	1796	0	0
intr_enable_rd_A	2147483647	2217	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2446	0	0
T3	473034	27	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	19	0	0
T13	0	51	0	0
T14	0	21	0	0
T15	0	20	0	0
T16	0	16	0	0
T17	0	10	0	0
T18	0	18	0	0
T19	0	15	0	0
T20	0	16	0	0
T21	176707	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2389	0	0
T3	473034	32	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	25	0	0
T13	0	32	0	0
T14	0	19	0	0
T15	0	6	0	0
T16	0	12	0	0
T17	0	12	0	0
T18	0	17	0	0
T19	0	17	0	0
T20	0	11	0	0
T21	176707	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2412	0	0
T3	473034	19	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	13	0	0
T13	0	44	0	0
T14	0	35	0	0
T15	0	21	0	0
T16	0	21	0	0
T17	0	29	0	0
T18	0	22	0	0
T19	0	20	0	0
T20	0	24	0	0
T21	176707	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2383	0	0
T3	473034	21	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	25	0	0
T13	0	28	0	0
T14	0	46	0	0
T15	0	8	0	0
T16	0	12	0	0
T17	0	24	0	0
T18	0	11	0	0
T19	0	16	0	0
T20	0	8	0	0
T21	176707	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2430	0	0
T3	473034	19	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	14	0	0
T13	0	22	0	0
T14	0	26	0	0
T15	0	24	0	0
T16	0	16	0	0
T17	0	21	0	0
T18	0	13	0	0
T19	0	25	0	0
T20	0	14	0	0
T21	176707	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2373	0	0
T3	473034	10	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	19	0	0
T13	0	27	0	0
T14	0	35	0	0
T15	0	15	0	0
T16	0	32	0	0
T17	0	19	0	0
T18	0	22	0	0
T19	0	20	0	0
T20	0	14	0	0
T21	176707	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2159	0	0
T3	473034	24	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	12	0	0
T13	0	26	0	0
T14	0	38	0	0
T15	0	13	0	0
T16	0	21	0	0
T17	0	14	0	0
T18	0	13	0	0
T19	0	24	0	0
T20	0	23	0	0
T21	176707	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2420	0	0
T3	473034	19	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	13	0	0
T13	0	31	0	0
T14	0	30	0	0
T15	0	17	0	0
T16	0	13	0	0
T17	0	5	0	0
T18	0	19	0	0
T19	0	24	0	0
T20	0	14	0	0
T21	176707	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2398	0	0
T3	473034	11	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	19	0	0
T13	0	27	0	0
T14	0	23	0	0
T15	0	23	0	0
T16	0	12	0	0
T17	0	11	0	0
T18	0	19	0	0
T19	0	15	0	0
T20	0	25	0	0
T21	176707	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2177	0	0
T3	473034	9	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	19	0	0
T13	0	29	0	0
T14	0	42	0	0
T15	0	13	0	0
T16	0	14	0	0
T17	0	27	0	0
T18	0	9	0	0
T19	0	17	0	0
T20	0	37	0	0
T21	176707	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2438	0	0
T3	473034	35	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	14	0	0
T13	0	21	0	0
T14	0	31	0	0
T15	0	13	0	0
T16	0	18	0	0
T17	0	17	0	0
T18	0	15	0	0
T19	0	25	0	0
T20	0	24	0	0
T21	176707	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2594	0	0
T3	473034	19	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	18	0	0
T13	0	38	0	0
T14	0	26	0	0
T15	0	12	0	0
T16	0	15	0	0
T17	0	16	0	0
T18	0	34	0	0
T19	0	20	0	0
T20	0	22	0	0
T21	176707	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2521	0	0
T3	473034	31	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	20	0	0
T13	0	40	0	0
T14	0	31	0	0
T15	0	17	0	0
T16	0	23	0	0
T17	0	15	0	0
T18	0	16	0	0
T19	0	13	0	0
T20	0	14	0	0
T21	176707	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2223	0	0
T3	473034	20	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	11	0	0
T13	0	28	0	0
T14	0	38	0	0
T15	0	16	0	0
T16	0	16	0	0
T17	0	13	0	0
T18	0	13	0	0
T19	0	18	0	0
T20	0	14	0	0
T21	176707	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2465	0	0
T3	473034	23	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	12	0	0
T13	0	34	0	0
T14	0	43	0	0
T15	0	11	0	0
T16	0	11	0	0
T17	0	22	0	0
T18	0	11	0	0
T19	0	25	0	0
T20	0	13	0	0
T21	176707	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2384	0	0
T3	473034	29	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	16	0	0
T13	0	36	0	0
T14	0	30	0	0
T15	0	12	0	0
T16	0	29	0	0
T17	0	14	0	0
T18	0	11	0	0
T19	0	28	0	0
T20	0	23	0	0
T21	176707	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1915	0	0
T3	473034	22	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	25	0	0
T13	0	34	0	0
T14	0	26	0	0
T15	0	20	0	0
T16	0	15	0	0
T17	0	16	0	0
T18	0	28	0	0
T19	0	21	0	0
T20	0	14	0	0
T21	176707	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1662	0	0
T3	473034	16	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	3	0	0
T13	0	20	0	0
T14	0	42	0	0
T15	0	13	0	0
T16	0	13	0	0
T17	0	13	0	0
T18	0	8	0	0
T19	0	17	0	0
T20	0	37	0	0
T21	176707	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2140	0	0
T3	473034	20	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	10	0	0
T13	0	33	0	0
T14	0	37	0	0
T15	0	10	0	0
T16	0	20	0	0
T17	0	27	0	0
T18	0	29	0	0
T19	0	24	0	0
T20	0	15	0	0
T21	176707	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1775	0	0
T3	473034	22	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	10	0	0
T13	0	11	0	0
T14	0	50	0	0
T15	0	15	0	0
T16	0	21	0	0
T17	0	5	0	0
T18	0	20	0	0
T19	0	22	0	0
T20	0	9	0	0
T21	176707	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2061	0	0
T3	473034	25	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	23	0	0
T13	0	36	0	0
T14	0	32	0	0
T15	0	13	0	0
T16	0	31	0	0
T17	0	16	0	0
T18	0	15	0	0
T19	0	14	0	0
T20	0	17	0	0
T21	176707	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1717	0	0
T3	473034	14	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	27	0	0
T13	0	46	0	0
T14	0	39	0	0
T15	0	29	0	0
T16	0	19	0	0
T17	0	13	0	0
T18	0	28	0	0
T19	0	13	0	0
T20	0	26	0	0
T21	176707	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1796	0	0
T3	473034	22	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	11	0	0
T13	0	25	0	0
T14	0	45	0	0
T15	0	7	0	0
T16	0	22	0	0
T17	0	14	0	0
T18	0	18	0	0
T19	0	14	0	0
T20	0	13	0	0
T21	176707	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2217	0	0
T3	473034	32	0	0
T4	794702	0	0	0
T5	279303	0	0	0
T6	818944	0	0	0
T7	821017	0	0	0
T8	378220	0	0	0
T9	166191	0	0	0
T10	611403	0	0	0
T11	352887	0	0	0
T12	0	16	0	0
T13	0	57	0	0
T14	0	28	0	0
T15	0	57	0	0
T16	0	45	0	0
T17	0	25	0	0
T21	176707	0	0	0
T22	0	17	0	0
T23	0	12	0	0
T24	0	4	0	0