Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1235253	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1208628

1

T1

72

T2

6295

T3

1394

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2151296	1			T1	81		T2	11976		T3	2480
values[0x0]	146084	1			T1	38		T2	380		T3	158
values[0x1]	146501	1			T1	25		T2	376		T3	151

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	989629	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1454252

1

T1

87

T2

7607

T3

1677

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8233	1			T2	14		T9	20		T11	2
valid_sources[0x01]	6741	1			T2	20		T7	5		T9	25
valid_sources[0x02]	8455	1			T2	16		T7	2		T9	3
valid_sources[0x03]	7701	1			T2	31		T7	12		T9	5
valid_sources[0x04]	7266	1			T2	15		T7	3		T9	9
valid_sources[0x05]	11706	1			T2	16		T9	12		T11	3
valid_sources[0x06]	13915	1			T2	44		T7	3		T9	17
valid_sources[0x07]	7423	1			T2	22		T7	4		T8	2
valid_sources[0x08]	7646	1			T2	64		T9	11		T10	1
valid_sources[0x09]	16399	1			T2	30		T7	1		T9	1
valid_sources[0x0a]	8470	1			T2	48		T7	2		T9	21
valid_sources[0x0b]	8559	1			T2	13		T7	4		T9	10
valid_sources[0x0c]	7125	1			T2	38		T7	8		T11	8
valid_sources[0x0d]	7531	1			T2	16		T7	3		T9	10
valid_sources[0x0e]	7343	1			T2	43		T7	1		T9	16
valid_sources[0x0f]	12235	1			T2	16		T7	2		T8	2
valid_sources[0x10]	7099	1			T2	59		T7	1		T9	6
valid_sources[0x11]	8178	1			T2	72		T7	4		T9	14
valid_sources[0x12]	8083	1			T2	28		T7	7		T9	3
valid_sources[0x13]	8054	1			T2	32		T7	7		T8	1
valid_sources[0x14]	20402	1			T2	37		T7	14		T8	1
valid_sources[0x15]	12089	1			T2	52		T9	9		T11	4
valid_sources[0x16]	8665	1			T2	36		T7	4		T9	10
valid_sources[0x17]	9957	1			T2	20		T7	4		T8	1
valid_sources[0x18]	12024	1			T2	34		T9	3		T11	2
valid_sources[0x19]	8084	1			T2	18		T9	10		T11	17
valid_sources[0x1a]	7874	1			T2	23		T7	1		T9	21
valid_sources[0x1b]	11722	1			T2	56		T4	4236		T7	3
valid_sources[0x1c]	9746	1			T2	24		T3	2789		T7	1
valid_sources[0x1d]	9169	1			T2	24		T7	7		T16	1
valid_sources[0x1e]	11650	1			T2	31		T7	3		T9	20
valid_sources[0x1f]	11499	1			T2	18		T7	2		T8	1
valid_sources[0x20]	13776	1			T2	36		T8	1		T9	18
valid_sources[0x21]	7244	1			T2	26		T8	1		T9	11
valid_sources[0x22]	7535	1			T2	45		T7	5		T9	13
valid_sources[0x23]	7474	1			T2	27		T7	11		T8	1
valid_sources[0x24]	20962	1			T2	31		T7	2		T9	10
valid_sources[0x25]	7311	1			T2	36		T9	5		T11	7
valid_sources[0x26]	8111	1			T2	31		T8	1		T9	10
valid_sources[0x27]	8436	1			T2	36		T7	1		T8	1
valid_sources[0x28]	7584	1			T2	39		T7	5		T9	9
valid_sources[0x29]	16744	1			T2	45		T9	25		T11	8
valid_sources[0x2a]	11760	1			T2	15		T9	13		T11	5
valid_sources[0x2b]	8800	1			T2	15		T7	5		T9	9
valid_sources[0x2c]	7621	1			T2	39		T7	16		T9	2
valid_sources[0x2d]	7198	1			T2	27		T7	1		T8	2
valid_sources[0x2e]	10371	1			T2	24		T7	3		T9	24
valid_sources[0x2f]	11207	1			T2	27		T7	4		T9	7
valid_sources[0x30]	10462	1			T2	25		T7	1		T8	2
valid_sources[0x31]	7312	1			T2	43		T9	9		T11	9
valid_sources[0x32]	7165	1			T2	38		T7	5		T9	15
valid_sources[0x33]	8006	1			T2	50		T7	2		T9	15
valid_sources[0x34]	7374	1			T2	37		T7	3		T9	16
valid_sources[0x35]	12063	1			T2	42		T9	23		T11	5
valid_sources[0x36]	10144	1			T2	70		T7	8		T9	13
valid_sources[0x37]	9953	1			T2	18		T7	7		T16	4
valid_sources[0x38]	7860	1			T2	14		T7	1		T9	14
valid_sources[0x39]	7901	1			T2	32		T7	4		T9	6
valid_sources[0x3a]	7604	1			T2	27		T7	6		T9	10
valid_sources[0x3b]	8048	1			T2	33		T7	4		T9	4
valid_sources[0x3c]	7316	1			T2	71		T7	11		T9	24
valid_sources[0x3d]	11543	1			T2	17		T7	1		T9	10
valid_sources[0x3e]	7273	1			T2	15		T5	37		T7	2
valid_sources[0x3f]	9829	1			T2	37		T7	3		T9	6
valid_sources[0x40]	8360	1			T2	34		T7	2		T9	12
valid_sources[0x41]	11494	1			T2	25		T7	4		T9	13
valid_sources[0x42]	7041	1			T2	20		T7	7		T11	9
valid_sources[0x43]	7304	1			T2	23		T7	6		T9	8
valid_sources[0x44]	14361	1			T2	41		T7	1		T9	11
valid_sources[0x45]	6742	1			T2	50		T8	1		T9	18
valid_sources[0x46]	7457	1			T2	19		T9	10		T10	1
valid_sources[0x47]	7099	1			T2	30		T9	21		T11	6
valid_sources[0x48]	8987	1			T2	23		T7	7		T9	4
valid_sources[0x49]	19835	1			T2	26		T8	1		T9	11
valid_sources[0x4a]	7759	1			T2	38		T9	11		T11	9
valid_sources[0x4b]	7344	1			T2	14		T7	18		T9	5
valid_sources[0x4c]	11725	1			T2	66		T7	1		T11	4
valid_sources[0x4d]	15654	1			T2	13		T7	8		T9	8
valid_sources[0x4e]	10372	1			T2	16		T7	6		T9	5
valid_sources[0x4f]	8227	1			T2	42		T7	12		T8	1
valid_sources[0x50]	7437	1			T2	12		T7	3		T9	11
valid_sources[0x51]	11272	1			T2	43		T7	1		T9	6
valid_sources[0x52]	7330	1			T2	23		T7	10		T9	4
valid_sources[0x53]	6982	1			T2	41		T7	3		T9	3
valid_sources[0x54]	7399	1			T2	28		T7	3		T9	5
valid_sources[0x55]	7585	1			T2	57		T7	2		T9	11
valid_sources[0x56]	7311	1			T2	28		T7	7		T9	23
valid_sources[0x57]	7728	1			T2	13		T9	7		T11	15
valid_sources[0x58]	8035	1			T2	36		T7	2		T8	1
valid_sources[0x59]	8471	1			T2	16		T7	15		T9	14
valid_sources[0x5a]	7397	1			T2	65		T8	1		T9	13
valid_sources[0x5b]	8259	1			T2	69		T7	1		T9	4
valid_sources[0x5c]	7825	1			T2	50		T7	4		T9	27
valid_sources[0x5d]	9015	1			T2	38		T7	10		T9	16
valid_sources[0x5e]	12144	1			T2	23		T7	2		T9	10
valid_sources[0x5f]	6970	1			T2	59		T7	1		T9	10
valid_sources[0x60]	12422	1			T2	41		T7	4		T9	9
valid_sources[0x61]	7391	1			T2	40		T7	6		T9	9
valid_sources[0x62]	7120	1			T2	23		T7	2		T9	3
valid_sources[0x63]	7266	1			T2	30		T7	3		T9	7
valid_sources[0x64]	7161	1			T2	45		T9	9		T11	3
valid_sources[0x65]	9507	1			T2	16		T7	2		T9	8
valid_sources[0x66]	8088	1			T2	28		T7	1		T9	25
valid_sources[0x67]	8244	1			T2	21		T6	1006		T7	2
valid_sources[0x68]	7314	1			T2	29		T7	4		T9	1
valid_sources[0x69]	23023	1			T2	22		T7	16		T9	14
valid_sources[0x6a]	7222	1			T2	46		T7	9		T8	1
valid_sources[0x6b]	16146	1			T2	42		T7	7		T9	16
valid_sources[0x6c]	8129	1			T2	23		T7	8		T9	17
valid_sources[0x6d]	7380	1			T2	36		T7	6		T9	13
valid_sources[0x6e]	7328	1			T2	15		T7	1		T9	11
valid_sources[0x6f]	11930	1			T2	34		T7	6		T9	5
valid_sources[0x70]	11680	1			T2	32		T7	3		T8	1
valid_sources[0x71]	7115	1			T2	53		T9	5		T11	3
valid_sources[0x72]	8205	1			T2	28		T7	4		T9	16
valid_sources[0x73]	11327	1			T2	35		T7	1		T9	11
valid_sources[0x74]	7537	1			T2	48		T8	1		T9	7
valid_sources[0x75]	8215	1			T2	19		T7	6		T9	9
valid_sources[0x76]	8409	1			T2	16		T7	1		T9	16
valid_sources[0x77]	11319	1			T2	23		T7	5		T8	2
valid_sources[0x78]	10602	1			T2	29		T7	4		T8	1
valid_sources[0x79]	9506	1			T2	27		T7	1		T9	10
valid_sources[0x7a]	7191	1			T2	23		T7	8		T9	9
valid_sources[0x7b]	7366	1			T2	20		T7	4		T9	3
valid_sources[0x7c]	11717	1			T2	27		T7	1		T9	21
valid_sources[0x7d]	7352	1			T2	29		T7	7		T8	1
valid_sources[0x7e]	13022	1			T2	75		T7	2		T9	4
valid_sources[0x7f]	8033	1			T2	22		T7	15		T9	2
valid_sources[0x80]	9879	1			T2	25		T8	3		T9	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1073035

1

T1

44

T2

6006

T3

1243

values[0x0]

all_enables

biggest_size

79018

1

T1

21

T2

183

T3

85

values[0x1]

all_enables

biggest_size

56575

1

T1

7

T2

106

T3

66