Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30294	1			T2	17		T3	21		T4	9
auto[PWRUP]	108	1			T6	1		T45	1		T46	3
auto[ONEST_0]	68	1			T6	2		T45	1		T46	1
auto[ONEST_021]	18	1			T6	1		T37	1		T47	3
auto[ONEST_1]	66	1			T6	2		T45	2		T46	1
auto[ONEST_DONE]	3	1			T156	1		T185	1		T186	1
auto[LP_0]	114	1			T6	2		T45	1		T46	4
auto[LP_021]	31	1			T47	1		T187	2		T50	1
auto[LP_1]	123	1			T6	1		T45	2		T46	3
auto[LP_EVAL]	77	1			T6	1		T45	1		T46	1
auto[LP_SLP]	508	1			T6	4		T45	5		T46	5
auto[LP_PWRUP]	20	1			T45	1		T46	1		T47	1
auto[NP_0]	163	1			T6	4		T45	4		T37	2
auto[NP_021]	36	1			T6	1		T45	2		T37	1
auto[NP_1]	146	1			T6	3		T45	1		T46	3
auto[NP_EVAL]	35	1			T37	2		T48	1		T84	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

3

1

T46

1

T188

1

T189

1

min

29835

1

T2

17

T3

21

T4

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29843	1			T2	17		T3	21		T4	9
pow[0x1]	5	1			T156	1		T50	1		T190	1
pow[0x2]	16	1			T6	1		T47	1		T51	2
pow[0x3]	37	1			T46	1		T47	1		T156	2
pow[0x4]	53	1			T6	2		T45	2		T37	4
pow[0x5]	123	1			T6	1		T45	3		T37	3
pow[0x6]	263	1			T6	5		T45	1		T46	7
pow[0x7]	480	1			T6	10		T45	8		T46	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

191

1

T6

4

T45

2

T46

5

min

29379

1

T2

17

T3

21

T4

9

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29379	1			T2	17		T3	21		T4	9
pow[0x3]	1	1			T88	1		-	-		-	-
pow[0x4]	1	1			T187	1		-	-		-	-
pow[0x5]	4	1			T37	1		T84	1		T51	1
pow[0x7]	4	1			T22	1		T191	1		T192	1
pow[0x8]	6	1			T37	1		T47	1		T51	1
pow[0x9]	11	1			T48	1		T188	2		T193	1
pow[0xa]	12	1			T46	1		T37	1		T17	1
pow[0xb]	33	1			T45	1		T46	1		T37	1
pow[0xc]	64	1			T6	2		T46	1		T37	1
pow[0xd]	150	1			T6	1		T45	2		T46	4
pow[0xe]	284	1			T6	2		T45	5		T46	6
pow[0xf]	547	1			T6	9		T45	3		T46	9