Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2149	1			T6	17		T45	27		T49	2
auto[PWRUP]	132	1			T6	3		T46	1		T37	4
auto[ONEST_0]	87	1			T6	1		T45	1		T37	2
auto[ONEST_021]	15	1			T156	1		T210	1		T346	1
auto[ONEST_1]	85	1			T6	2		T37	3		T48	1
auto[ONEST_DONE]	1	1			T347	1		-	-		-	-
auto[LP_0]	138	1			T6	1		T45	1		T46	1
auto[LP_021]	29	1			T37	1		T48	2		T156	1
auto[LP_1]	131	1			T6	2		T45	1		T46	2
auto[LP_EVAL]	68	1			T46	1		T37	3		T17	1
auto[LP_SLP]	472	1			T6	7		T45	6		T46	9
auto[LP_PWRUP]	30	1			T6	1		T45	1		T84	1
auto[NP_0]	222	1			T6	1		T45	4		T46	3
auto[NP_021]	55	1			T46	1		T37	2		T17	1
auto[NP_1]	194	1			T6	5		T45	2		T46	1
auto[NP_EVAL]	32	1			T17	1		T47	1		T38	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T37

1

T47

1

T187

1

min

1836

1

T6

10

T45

8

T49

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1846	1			T6	10		T45	8		T49	2
pow[0x1]	10	1			T45	1		T297	1		T22	1
pow[0x2]	24	1			T47	1		T84	1		T348	1
pow[0x3]	35	1			T47	1		T84	1		T21	1
pow[0x4]	82	1			T6	3		T45	1		T37	2
pow[0x5]	124	1			T6	2		T45	1		T46	2
pow[0x6]	257	1			T6	3		T45	7		T46	5
pow[0x7]	488	1			T6	6		T45	10		T46	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

221

1

T6

2

T45

1

T46

6

min

1280

1

T6

4

T45

5

T49

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1286	1			T6	4		T45	5		T49	2
pow[0x1]	15	1			T37	1		T38	1		T210	2
pow[0x2]	29	1			T21	2		T194	1		T297	2
pow[0x3]	34	1			T37	2		T17	4		T38	2
pow[0x4]	49	1			T39	2		T21	3		T194	2
pow[0x5]	1	1			T349	1		-	-		-	-
pow[0x7]	5	1			T37	1		T350	1		T321	1
pow[0x8]	8	1			T37	1		T51	1		T351	1
pow[0x9]	9	1			T48	1		T346	1		T23	1
pow[0xa]	13	1			T37	1		T321	1		T352	1
pow[0xb]	30	1			T47	1		T48	1		T187	1
pow[0xc]	66	1			T37	2		T17	1		T156	3
pow[0xd]	152	1			T6	3		T45	6		T46	3
pow[0xe]	252	1			T6	4		T45	3		T46	4
pow[0xf]	517	1			T6	6		T45	12		T46	6