Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1605	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1680	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1569	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1735	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1641	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1528	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1547	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1579	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1593	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1602	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1619	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1743	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1800	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1494	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1631	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1701	0	0
adc_en_ctl_rd_A	2147483647	1333	0	0
adc_fsm_rst_rd_A	2147483647	1170	0	0
adc_intr_ctl_rd_A	2147483647	1461	0	0
adc_lp_sample_ctl_rd_A	2147483647	1184	0	0
adc_pd_ctl_rd_A	2147483647	1326	0	0
adc_sample_ctl_rd_A	2147483647	1198	0	0
adc_wakeup_ctl_rd_A	2147483647	1299	0	0
intr_enable_rd_A	2147483647	1598	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1605	0	0
T17	650908	18	0	0
T18	0	22	0	0
T19	0	28	0	0
T20	0	25	0	0
T21	0	42	0	0
T22	0	5	0	0
T23	0	48	0	0
T24	0	20	0	0
T25	0	17	0	0
T26	0	13	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1680	0	0
T17	650908	21	0	0
T18	0	24	0	0
T19	0	22	0	0
T20	0	14	0	0
T21	0	32	0	0
T22	0	12	0	0
T23	0	37	0	0
T24	0	13	0	0
T25	0	28	0	0
T26	0	8	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1569	0	0
T17	650908	16	0	0
T18	0	27	0	0
T19	0	14	0	0
T20	0	10	0	0
T21	0	25	0	0
T22	0	5	0	0
T23	0	32	0	0
T24	0	7	0	0
T25	0	31	0	0
T26	0	14	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1735	0	0
T17	650908	21	0	0
T18	0	24	0	0
T19	0	22	0	0
T20	0	13	0	0
T21	0	34	0	0
T22	0	2	0	0
T23	0	58	0	0
T24	0	19	0	0
T25	0	29	0	0
T26	0	10	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1641	0	0
T17	650908	17	0	0
T18	0	22	0	0
T19	0	28	0	0
T20	0	14	0	0
T21	0	20	0	0
T22	0	3	0	0
T23	0	37	0	0
T24	0	20	0	0
T25	0	41	0	0
T26	0	4	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1528	0	0
T17	650908	9	0	0
T18	0	12	0	0
T19	0	20	0	0
T20	0	27	0	0
T21	0	27	0	0
T22	0	2	0	0
T23	0	42	0	0
T24	0	7	0	0
T25	0	29	0	0
T26	0	7	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1547	0	0
T17	650908	23	0	0
T18	0	18	0	0
T19	0	17	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	2	0	0
T23	0	35	0	0
T24	0	20	0	0
T25	0	25	0	0
T26	0	4	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1579	0	0
T17	650908	17	0	0
T18	0	14	0	0
T19	0	20	0	0
T20	0	30	0	0
T21	0	41	0	0
T22	0	9	0	0
T23	0	24	0	0
T24	0	22	0	0
T25	0	27	0	0
T26	0	15	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1593	0	0
T17	650908	26	0	0
T18	0	22	0	0
T19	0	13	0	0
T20	0	19	0	0
T21	0	37	0	0
T22	0	1	0	0
T23	0	23	0	0
T24	0	9	0	0
T25	0	19	0	0
T26	0	14	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1602	0	0
T17	650908	11	0	0
T18	0	19	0	0
T19	0	23	0	0
T20	0	23	0	0
T21	0	33	0	0
T22	0	4	0	0
T23	0	32	0	0
T24	0	18	0	0
T25	0	47	0	0
T26	0	20	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1619	0	0
T17	650908	17	0	0
T18	0	31	0	0
T19	0	24	0	0
T20	0	26	0	0
T21	0	33	0	0
T22	0	16	0	0
T23	0	26	0	0
T24	0	14	0	0
T25	0	20	0	0
T26	0	18	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1743	0	0
T17	650908	10	0	0
T18	0	24	0	0
T19	0	16	0	0
T20	0	11	0	0
T21	0	22	0	0
T22	0	11	0	0
T23	0	33	0	0
T24	0	18	0	0
T25	0	32	0	0
T26	0	13	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1800	0	0
T17	650908	21	0	0
T18	0	33	0	0
T19	0	17	0	0
T20	0	17	0	0
T21	0	26	0	0
T22	0	10	0	0
T23	0	46	0	0
T24	0	3	0	0
T25	0	31	0	0
T26	0	16	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1494	0	0
T17	650908	13	0	0
T18	0	26	0	0
T19	0	15	0	0
T20	0	19	0	0
T21	0	35	0	0
T22	0	9	0	0
T23	0	32	0	0
T24	0	12	0	0
T25	0	31	0	0
T26	0	17	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1631	0	0
T17	650908	20	0	0
T18	0	16	0	0
T19	0	22	0	0
T20	0	20	0	0
T21	0	36	0	0
T22	0	8	0	0
T23	0	41	0	0
T24	0	10	0	0
T25	0	16	0	0
T26	0	20	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1701	0	0
T17	650908	21	0	0
T18	0	16	0	0
T19	0	23	0	0
T20	0	25	0	0
T21	0	25	0	0
T22	0	11	0	0
T23	0	49	0	0
T24	0	14	0	0
T25	0	23	0	0
T26	0	21	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1333	0	0
T17	650908	13	0	0
T18	0	20	0	0
T19	0	17	0	0
T20	0	19	0	0
T21	0	30	0	0
T22	0	5	0	0
T23	0	33	0	0
T24	0	19	0	0
T25	0	23	0	0
T26	0	16	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1170	0	0
T17	650908	14	0	0
T18	0	24	0	0
T19	0	23	0	0
T20	0	19	0	0
T21	0	46	0	0
T22	0	2	0	0
T23	0	30	0	0
T24	0	12	0	0
T25	0	22	0	0
T26	0	5	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1461	0	0
T17	650908	35	0	0
T18	0	24	0	0
T19	0	23	0	0
T20	0	13	0	0
T21	0	30	0	0
T22	0	3	0	0
T23	0	25	0	0
T24	0	16	0	0
T25	0	11	0	0
T26	0	5	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1184	0	0
T17	650908	21	0	0
T18	0	14	0	0
T19	0	14	0	0
T20	0	8	0	0
T21	0	20	0	0
T22	0	5	0	0
T23	0	35	0	0
T24	0	14	0	0
T25	0	27	0	0
T26	0	17	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1326	0	0
T17	650908	16	0	0
T18	0	15	0	0
T19	0	21	0	0
T20	0	19	0	0
T21	0	34	0	0
T22	0	16	0	0
T23	0	41	0	0
T24	0	10	0	0
T25	0	19	0	0
T26	0	5	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1198	0	0
T17	650908	15	0	0
T18	0	23	0	0
T19	0	25	0	0
T20	0	15	0	0
T21	0	41	0	0
T22	0	19	0	0
T23	0	43	0	0
T24	0	13	0	0
T25	0	31	0	0
T26	0	5	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1299	0	0
T17	650908	21	0	0
T18	0	10	0	0
T19	0	17	0	0
T20	0	14	0	0
T21	0	27	0	0
T22	0	4	0	0
T23	0	30	0	0
T24	0	21	0	0
T25	0	25	0	0
T26	0	8	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1598	0	0
T17	650908	14	0	0
T18	0	38	0	0
T19	0	5	0	0
T20	0	23	0	0
T21	0	59	0	0
T22	0	19	0	0
T23	0	44	0	0
T24	0	24	0	0
T25	0	40	0	0
T27	117701	0	0	0
T28	244675	0	0	0
T29	561129	0	0	0
T30	355616	0	0	0
T31	125469	0	0	0
T32	557976	0	0	0
T33	472810	0	0	0
T34	412612	0	0	0
T35	163982	0	0	0
T36	0	31	0	0