Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1197391	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1171784

1

T1

21

T2

39

T3

4003

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2078310	1			T3	7516		T4	1677		T5	4848
values[0x0]	145192	1			T1	22		T2	28		T3	345
values[0x1]	145673	1			T1	15		T2	33		T3	351

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	959604	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1409571

1

T1

25

T2

46

T3

4832

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11803	1			T3	33		T4	1		T5	19
valid_sources[0x01]	12214	1			T3	31		T4	9		T5	25
valid_sources[0x02]	9803	1			T3	28		T4	8		T5	11
valid_sources[0x03]	7849	1			T3	34		T4	11		T5	19
valid_sources[0x04]	6390	1			T2	1		T3	34		T4	12
valid_sources[0x05]	12470	1			T1	1		T3	40		T4	6
valid_sources[0x06]	6385	1			T1	1		T3	31		T4	12
valid_sources[0x07]	6514	1			T3	28		T4	4		T5	18
valid_sources[0x08]	6766	1			T3	30		T4	10		T5	27
valid_sources[0x09]	12174	1			T3	28		T4	8		T5	22
valid_sources[0x0a]	9561	1			T3	32		T4	9		T5	25
valid_sources[0x0b]	9416	1			T3	23		T4	13		T5	25
valid_sources[0x0c]	6901	1			T3	37		T4	10		T5	11
valid_sources[0x0d]	6471	1			T3	34		T4	4		T5	19
valid_sources[0x0e]	12851	1			T3	30		T4	1		T5	12
valid_sources[0x0f]	9593	1			T2	1		T3	23		T4	3
valid_sources[0x10]	10722	1			T3	25		T4	19		T5	15
valid_sources[0x11]	6371	1			T3	39		T4	12		T5	8
valid_sources[0x12]	11451	1			T3	42		T4	2		T5	16
valid_sources[0x13]	7571	1			T3	31		T4	7		T5	38
valid_sources[0x14]	19288	1			T1	1		T3	33		T4	5
valid_sources[0x15]	6388	1			T3	33		T4	3		T5	31
valid_sources[0x16]	11541	1			T3	49		T4	8		T5	17
valid_sources[0x17]	6916	1			T3	27		T4	12		T5	31
valid_sources[0x18]	9539	1			T3	35		T4	4		T5	14
valid_sources[0x19]	6743	1			T3	27		T4	8		T5	17
valid_sources[0x1a]	19029	1			T3	38		T4	9		T5	24
valid_sources[0x1b]	6411	1			T3	24		T4	8		T5	15
valid_sources[0x1c]	6687	1			T3	41		T4	6		T5	33
valid_sources[0x1d]	14668	1			T3	34		T4	2		T5	19
valid_sources[0x1e]	19841	1			T3	25		T4	12		T5	10
valid_sources[0x1f]	6523	1			T3	26		T4	4		T5	39
valid_sources[0x20]	12863	1			T3	40		T4	5		T5	25
valid_sources[0x21]	7299	1			T1	1		T3	34		T4	12
valid_sources[0x22]	9869	1			T3	31		T4	9		T5	28
valid_sources[0x23]	11449	1			T2	1		T3	47		T4	7
valid_sources[0x24]	11802	1			T2	1		T3	24		T4	6
valid_sources[0x25]	10154	1			T1	1		T3	31		T4	8
valid_sources[0x26]	7026	1			T3	29		T4	4		T5	8
valid_sources[0x27]	6614	1			T1	1		T3	29		T4	4
valid_sources[0x28]	7856	1			T3	33		T4	12		T5	34
valid_sources[0x29]	6581	1			T1	1		T3	35		T4	4
valid_sources[0x2a]	6409	1			T3	32		T4	1		T5	16
valid_sources[0x2b]	6783	1			T3	31		T4	4		T5	13
valid_sources[0x2c]	6999	1			T3	24		T4	6		T5	22
valid_sources[0x2d]	10818	1			T3	40		T4	1		T5	23
valid_sources[0x2e]	7804	1			T3	24		T4	8		T5	16
valid_sources[0x2f]	6843	1			T1	1		T3	26		T4	2
valid_sources[0x30]	16126	1			T3	29		T4	13		T5	17
valid_sources[0x31]	12020	1			T1	1		T3	19		T4	6
valid_sources[0x32]	20734	1			T2	1		T3	18		T4	9
valid_sources[0x33]	6669	1			T3	35		T4	4		T5	17
valid_sources[0x34]	6675	1			T3	39		T4	7		T5	47
valid_sources[0x35]	7003	1			T3	43		T4	9		T5	16
valid_sources[0x36]	10977	1			T2	1		T3	32		T4	8
valid_sources[0x37]	6427	1			T1	1		T3	24		T4	9
valid_sources[0x38]	6711	1			T2	1		T3	34		T4	4
valid_sources[0x39]	6689	1			T2	1		T3	36		T4	4
valid_sources[0x3a]	7353	1			T2	1		T3	35		T4	10
valid_sources[0x3b]	11630	1			T3	30		T4	12		T5	14
valid_sources[0x3c]	6446	1			T3	34		T4	9		T5	28
valid_sources[0x3d]	15230	1			T3	26		T4	6		T5	18
valid_sources[0x3e]	6585	1			T3	35		T4	14		T5	18
valid_sources[0x3f]	7299	1			T3	26		T4	3		T5	25
valid_sources[0x40]	9090	1			T2	1		T3	26		T4	5
valid_sources[0x41]	7310	1			T2	1		T3	52		T4	5
valid_sources[0x42]	7157	1			T3	27		T4	6		T5	16
valid_sources[0x43]	6827	1			T2	3		T3	34		T4	6
valid_sources[0x44]	6897	1			T3	38		T4	12		T5	19
valid_sources[0x45]	8112	1			T1	1		T3	18		T4	6
valid_sources[0x46]	6852	1			T3	29		T4	10		T5	34
valid_sources[0x47]	11148	1			T1	1		T3	26		T4	10
valid_sources[0x48]	12082	1			T3	46		T4	5		T5	34
valid_sources[0x49]	10915	1			T3	34		T4	12		T5	25
valid_sources[0x4a]	9272	1			T2	2		T3	26		T4	4
valid_sources[0x4b]	7120	1			T3	39		T5	19		T7	1
valid_sources[0x4c]	6677	1			T3	26		T4	10		T5	13
valid_sources[0x4d]	15424	1			T3	40		T4	1		T5	15
valid_sources[0x4e]	7274	1			T3	30		T4	8		T5	10
valid_sources[0x4f]	6708	1			T3	30		T5	16		T6	34
valid_sources[0x50]	9105	1			T3	34		T4	4		T5	34
valid_sources[0x51]	7042	1			T3	19		T4	6		T5	17
valid_sources[0x52]	10755	1			T1	1		T3	26		T4	7
valid_sources[0x53]	22565	1			T3	40		T4	9		T5	18
valid_sources[0x54]	6821	1			T2	2		T3	50		T4	2
valid_sources[0x55]	15386	1			T2	1		T3	22		T4	6
valid_sources[0x56]	6595	1			T3	29		T4	6		T5	29
valid_sources[0x57]	20248	1			T3	34		T4	7		T5	15
valid_sources[0x58]	11824	1			T3	22		T4	9		T5	24
valid_sources[0x59]	6806	1			T3	48		T4	6		T5	13
valid_sources[0x5a]	7437	1			T3	30		T4	2		T5	20
valid_sources[0x5b]	9606	1			T3	30		T4	9		T5	19
valid_sources[0x5c]	7524	1			T3	32		T4	9		T5	20
valid_sources[0x5d]	7661	1			T3	22		T4	6		T5	19
valid_sources[0x5e]	6673	1			T3	33		T4	9		T5	15
valid_sources[0x5f]	11488	1			T3	41		T4	13		T5	27
valid_sources[0x60]	11022	1			T2	1		T3	34		T4	4
valid_sources[0x61]	10719	1			T2	2		T3	27		T4	9
valid_sources[0x62]	6440	1			T3	52		T4	10		T5	12
valid_sources[0x63]	6563	1			T3	21		T4	2		T5	19
valid_sources[0x64]	6797	1			T3	25		T4	6		T5	16
valid_sources[0x65]	6320	1			T3	35		T4	4		T5	18
valid_sources[0x66]	7350	1			T3	32		T4	11		T5	22
valid_sources[0x67]	7398	1			T3	23		T4	11		T5	26
valid_sources[0x68]	8428	1			T3	45		T4	13		T5	24
valid_sources[0x69]	8729	1			T2	1		T3	32		T4	4
valid_sources[0x6a]	6692	1			T3	30		T4	8		T5	22
valid_sources[0x6b]	10349	1			T1	2		T3	27		T4	4
valid_sources[0x6c]	7128	1			T3	27		T4	7		T5	22
valid_sources[0x6d]	8378	1			T3	48		T4	4		T5	14
valid_sources[0x6e]	14916	1			T3	31		T4	6		T5	28
valid_sources[0x6f]	7354	1			T3	50		T4	4		T5	14
valid_sources[0x70]	8922	1			T3	31		T4	9		T5	23
valid_sources[0x71]	7395	1			T3	33		T4	6		T5	14
valid_sources[0x72]	6731	1			T3	42		T4	4		T5	15
valid_sources[0x73]	6914	1			T3	38		T4	6		T5	13
valid_sources[0x74]	6899	1			T2	1		T3	41		T4	5
valid_sources[0x75]	13710	1			T3	41		T4	2		T5	12
valid_sources[0x76]	9072	1			T3	30		T4	5		T5	14
valid_sources[0x77]	6463	1			T3	34		T4	7		T5	26
valid_sources[0x78]	7201	1			T3	23		T4	6		T5	33
valid_sources[0x79]	6803	1			T3	37		T4	10		T5	17
valid_sources[0x7a]	6397	1			T3	26		T4	4		T5	7
valid_sources[0x7b]	7233	1			T3	35		T4	9		T5	39
valid_sources[0x7c]	8711	1			T3	35		T4	5		T5	11
valid_sources[0x7d]	10609	1			T2	1		T3	25		T4	10
valid_sources[0x7e]	13548	1			T3	37		T4	12		T5	25
valid_sources[0x7f]	8292	1			T3	37		T4	9		T5	17
valid_sources[0x80]	12845	1			T2	1		T3	33		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1035319

1

T3

3729

T4

813

T5

2441

values[0x0]

all_enables

biggest_size

79230

1

T1

14

T2

20

T3

174

values[0x1]

all_enables

biggest_size

57235

1

T1

7

T2

19

T3

100