Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
88.89 88.89 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_fsm_reset_cg_inst 88.89 1 100 1 64 64




Group Instance : adc_ctrl_fsm_reset_cg_inst
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
88.89 1 100 1 64 64




Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 45 5 40 88.89


Variables for Group Instance adc_ctrl_fsm_reset_cg_inst
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
fsm_state_cp 17 1 16 94.12 100 1 1 0
lp_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
lp_sample_cnt_pow_cp 8 0 8 100.00 100 1 1 0
np_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
np_sample_cnt_pow_cp 16 4 12 75.00 100 1 1 0


Summary for Variable fsm_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 17 1 16 94.12


Automatically Generated Bins for fsm_state_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[NP_DONE] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[PWRDN] 26973 1 T3 22 T4 14 T5 17
auto[PWRUP] 100 1 T11 2 T44 3 T36 2
auto[ONEST_0] 73 1 T41 1 T40 2 T45 1
auto[ONEST_021] 17 1 T7 1 T43 1 T225 1
auto[ONEST_1] 77 1 T7 3 T44 1 T41 1
auto[ONEST_DONE] 3 1 T226 1 T227 1 T228 1
auto[LP_0] 119 1 T11 2 T44 1 T41 1
auto[LP_021] 26 1 T41 1 T42 1 T43 1
auto[LP_1] 131 1 T7 1 T11 6 T44 1
auto[LP_EVAL] 69 1 T44 1 T41 1 T40 3
auto[LP_SLP] 485 1 T7 1 T11 10 T15 1
auto[LP_PWRUP] 26 1 T41 1 T229 1 T230 1
auto[NP_0] 136 1 T11 2 T44 2 T41 1
auto[NP_021] 22 1 T43 2 T229 1 T230 1
auto[NP_1] 129 1 T7 1 T11 1 T41 2
auto[NP_EVAL] 27 1 T11 1 T40 1 T231 1



Summary for Variable lp_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for lp_sample_cnt_min_max_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
max 10 1 T232 1 T225 1 T233 1
min 26484 1 T3 22 T4 14 T5 17



Summary for Variable lp_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for lp_sample_cnt_pow_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
pow[0x0] 26489 1 T3 22 T4 14 T5 17
pow[0x1] 7 1 T42 1 T45 1 T234 1
pow[0x2] 10 1 T41 1 T235 1 T236 2
pow[0x3] 32 1 T44 1 T231 3 T237 1
pow[0x4] 58 1 T41 2 T36 1 T42 1
pow[0x5] 110 1 T11 2 T44 1 T40 1
pow[0x6] 248 1 T7 3 T11 5 T31 1
pow[0x7] 470 1 T7 2 T11 9 T31 1



Summary for Variable np_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for np_sample_cnt_min_max_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
max 169 1 T7 1 T11 3 T44 1
min 26001 1 T3 22 T4 14 T5 17



Summary for Variable np_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 16 4 12 75.00


User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
pow[0x1] 0 1 1
pow[0x2] 0 1 1
pow[0x4] 0 1 1
pow[0x5] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
pow[0x0] 26001 1 T3 22 T4 14 T5 17
pow[0x3] 1 1 T238 1 - - - -
pow[0x6] 2 1 T238 1 T239 1 - -
pow[0x7] 1 1 T240 1 - - - -
pow[0x8] 8 1 T33 1 T234 1 T82 1
pow[0x9] 7 1 T226 1 T241 1 T233 1
pow[0xa] 18 1 T11 1 T45 1 T242 1
pow[0xb] 42 1 T11 1 T36 1 T42 2
pow[0xc] 67 1 T7 1 T11 3 T44 2
pow[0xd] 130 1 T7 1 T11 1 T44 2
pow[0xe] 309 1 T11 5 T15 1 T44 4
pow[0xf] 560 1 T7 3 T11 8 T31 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%