Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2149	1			T7	18		T11	13		T15	10
auto[PWRUP]	131	1			T7	2		T11	1		T13	1
auto[ONEST_0]	68	1			T7	1		T229	1		T230	1
auto[ONEST_021]	10	1			T11	1		T230	1		T231	1
auto[ONEST_1]	90	1			T7	1		T31	1		T44	2
auto[ONEST_DONE]	7	1			T230	1		T237	1		T366	1
auto[LP_0]	132	1			T31	2		T44	2		T41	3
auto[LP_021]	18	1			T230	2		T366	1		T18	2
auto[LP_1]	130	1			T7	1		T11	3		T41	2
auto[LP_EVAL]	57	1			T15	1		T36	2		T40	1
auto[LP_SLP]	475	1			T11	8		T15	3		T13	1
auto[LP_PWRUP]	26	1			T31	1		T45	1		T367	1
auto[NP_0]	215	1			T7	4		T11	2		T15	1
auto[NP_021]	45	1			T7	1		T44	1		T41	2
auto[NP_1]	215	1			T7	4		T11	1		T31	2
auto[NP_EVAL]	31	1			T31	1		T275	3		T263	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T368

1

T369

1

T33

1

min

1812

1

T7

25

T11

8

T15

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1826	1			T7	25		T11	8		T15	9
pow[0x1]	16	1			T31	1		T298	1		T18	1
pow[0x2]	14	1			T31	1		T44	1		T146	1
pow[0x3]	43	1			T11	1		T44	1		T39	1
pow[0x4]	65	1			T41	2		T40	2		T42	3
pow[0x5]	138	1			T44	2		T41	1		T36	1
pow[0x6]	223	1			T11	3		T31	2		T41	4
pow[0x7]	450	1			T7	3		T11	2		T15	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

195

1

T11

2

T15

1

T31

1

min

1261

1

T7

23

T11

2

T15

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1267	1			T7	24		T11	2		T15	6
pow[0x1]	19	1			T7	1		T31	1		T36	3
pow[0x2]	17	1			T38	2		T275	6		T263	3
pow[0x3]	41	1			T31	1		T37	2		T39	1
pow[0x4]	63	1			T7	2		T13	1		T16	2
pow[0x6]	2	1			T232	1		T35	1		-	-
pow[0x7]	1	1			T230	1		-	-		-	-
pow[0x8]	7	1			T11	1		T43	1		T231	1
pow[0x9]	6	1			T11	1		T366	1		T226	1
pow[0xa]	14	1			T43	1		T367	1		T366	1
pow[0xb]	35	1			T11	1		T41	2		T36	1
pow[0xc]	66	1			T41	1		T36	3		T42	1
pow[0xd]	141	1			T11	2		T41	3		T42	1
pow[0xe]	276	1			T7	1		T11	5		T15	2
pow[0xf]	538	1			T7	1		T11	5		T15	3