Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2115	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2053	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2047	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2277	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2156	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1906	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2075	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2189	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2067	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2036	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2295	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2209	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2047	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2047	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2283	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1926	0	0
adc_en_ctl_rd_A	2147483647	1861	0	0
adc_fsm_rst_rd_A	2147483647	1826	0	0
adc_intr_ctl_rd_A	2147483647	2161	0	0
adc_lp_sample_ctl_rd_A	2147483647	1772	0	0
adc_pd_ctl_rd_A	2147483647	1816	0	0
adc_sample_ctl_rd_A	2147483647	1674	0	0
adc_wakeup_ctl_rd_A	2147483647	1850	0	0
intr_enable_rd_A	2147483647	2366	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2115	0	0
T13	232902	12	0	0
T15	102810	35	0	0
T16	0	12	0	0
T17	0	35	0	0
T18	0	17	0	0
T19	0	16	0	0
T20	0	14	0	0
T21	0	10	0	0
T22	0	34	0	0
T23	0	39	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2053	0	0
T13	232902	27	0	0
T15	102810	18	0	0
T16	0	28	0	0
T17	0	19	0	0
T18	0	12	0	0
T19	0	19	0	0
T20	0	24	0	0
T21	0	11	0	0
T22	0	31	0	0
T23	0	51	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2047	0	0
T13	232902	10	0	0
T15	102810	21	0	0
T16	0	10	0	0
T17	0	44	0	0
T18	0	21	0	0
T19	0	17	0	0
T20	0	18	0	0
T21	0	7	0	0
T22	0	35	0	0
T23	0	43	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2277	0	0
T13	232902	20	0	0
T15	102810	11	0	0
T16	0	9	0	0
T17	0	20	0	0
T18	0	25	0	0
T19	0	20	0	0
T20	0	9	0	0
T21	0	9	0	0
T22	0	47	0	0
T23	0	23	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2156	0	0
T13	232902	14	0	0
T15	102810	23	0	0
T16	0	5	0	0
T17	0	29	0	0
T18	0	6	0	0
T19	0	9	0	0
T20	0	19	0	0
T21	0	9	0	0
T22	0	38	0	0
T23	0	46	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1906	0	0
T13	232902	17	0	0
T15	102810	11	0	0
T16	0	17	0	0
T17	0	25	0	0
T18	0	15	0	0
T19	0	18	0	0
T20	0	22	0	0
T21	0	13	0	0
T22	0	29	0	0
T23	0	7	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2075	0	0
T13	232902	14	0	0
T15	102810	10	0	0
T16	0	22	0	0
T17	0	29	0	0
T18	0	26	0	0
T19	0	18	0	0
T20	0	22	0	0
T21	0	7	0	0
T22	0	54	0	0
T23	0	30	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2189	0	0
T13	232902	11	0	0
T15	102810	27	0	0
T16	0	9	0	0
T17	0	24	0	0
T18	0	25	0	0
T19	0	10	0	0
T20	0	16	0	0
T21	0	4	0	0
T22	0	48	0	0
T23	0	23	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2067	0	0
T13	232902	20	0	0
T15	102810	24	0	0
T16	0	19	0	0
T17	0	23	0	0
T18	0	23	0	0
T19	0	24	0	0
T20	0	17	0	0
T21	0	13	0	0
T22	0	54	0	0
T23	0	9	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2036	0	0
T13	232902	19	0	0
T15	102810	25	0	0
T16	0	16	0	0
T17	0	40	0	0
T18	0	29	0	0
T19	0	17	0	0
T20	0	20	0	0
T21	0	6	0	0
T22	0	27	0	0
T23	0	14	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2295	0	0
T13	232902	18	0	0
T15	102810	11	0	0
T16	0	14	0	0
T17	0	24	0	0
T18	0	25	0	0
T19	0	20	0	0
T20	0	20	0	0
T21	0	11	0	0
T22	0	40	0	0
T23	0	52	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2209	0	0
T13	232902	33	0	0
T15	102810	20	0	0
T16	0	19	0	0
T17	0	24	0	0
T18	0	30	0	0
T19	0	18	0	0
T20	0	19	0	0
T21	0	18	0	0
T22	0	35	0	0
T23	0	20	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2047	0	0
T13	232902	27	0	0
T15	102810	14	0	0
T16	0	15	0	0
T17	0	17	0	0
T18	0	24	0	0
T19	0	26	0	0
T20	0	21	0	0
T21	0	22	0	0
T22	0	39	0	0
T23	0	5	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2047	0	0
T13	232902	15	0	0
T15	102810	24	0	0
T16	0	19	0	0
T17	0	27	0	0
T18	0	12	0	0
T19	0	16	0	0
T20	0	21	0	0
T21	0	10	0	0
T22	0	37	0	0
T23	0	33	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2283	0	0
T13	232902	13	0	0
T15	102810	24	0	0
T16	0	11	0	0
T17	0	35	0	0
T18	0	29	0	0
T19	0	17	0	0
T20	0	18	0	0
T21	0	15	0	0
T22	0	12	0	0
T23	0	38	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1926	0	0
T13	232902	9	0	0
T15	102810	24	0	0
T16	0	15	0	0
T17	0	43	0	0
T18	0	24	0	0
T19	0	33	0	0
T20	0	19	0	0
T21	0	14	0	0
T22	0	18	0	0
T23	0	13	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1861	0	0
T13	232902	14	0	0
T15	102810	15	0	0
T16	0	13	0	0
T17	0	43	0	0
T18	0	26	0	0
T19	0	27	0	0
T20	0	11	0	0
T21	0	10	0	0
T22	0	31	0	0
T23	0	9	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1826	0	0
T13	232902	19	0	0
T15	102810	27	0	0
T16	0	12	0	0
T17	0	43	0	0
T18	0	16	0	0
T19	0	16	0	0
T20	0	11	0	0
T21	0	6	0	0
T22	0	31	0	0
T23	0	15	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2161	0	0
T13	232902	20	0	0
T15	102810	7	0	0
T16	0	13	0	0
T17	0	41	0	0
T18	0	32	0	0
T19	0	30	0	0
T20	0	15	0	0
T21	0	20	0	0
T22	0	31	0	0
T23	0	44	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1772	0	0
T13	232902	31	0	0
T15	102810	11	0	0
T16	0	19	0	0
T17	0	45	0	0
T18	0	4	0	0
T19	0	15	0	0
T20	0	23	0	0
T21	0	13	0	0
T22	0	27	0	0
T23	0	5	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1816	0	0
T13	232902	7	0	0
T15	102810	20	0	0
T16	0	16	0	0
T17	0	18	0	0
T18	0	18	0	0
T19	0	16	0	0
T20	0	22	0	0
T21	0	6	0	0
T22	0	39	0	0
T23	0	11	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1674	0	0
T13	232902	23	0	0
T15	102810	13	0	0
T16	0	20	0	0
T17	0	26	0	0
T18	0	30	0	0
T19	0	14	0	0
T20	0	24	0	0
T21	0	11	0	0
T22	0	43	0	0
T23	0	17	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1850	0	0
T13	232902	31	0	0
T15	102810	16	0	0
T16	0	13	0	0
T17	0	35	0	0
T18	0	14	0	0
T19	0	22	0	0
T20	0	23	0	0
T21	0	5	0	0
T22	0	38	0	0
T23	0	23	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2366	0	0
T13	232902	11	0	0
T15	102810	20	0	0
T16	0	41	0	0
T17	0	54	0	0
T18	0	19	0	0
T19	0	19	0	0
T24	386039	0	0	0
T25	221338	0	0	0
T26	273601	0	0	0
T27	31034	0	0	0
T28	848155	0	0	0
T29	853048	0	0	0
T30	133407	0	0	0
T31	484974	0	0	0
T32	0	15	0	0
T33	0	12	0	0
T34	0	25	0	0
T35	0	17	0	0