Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205436	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1176237

1

T1

898

T2

393

T4

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2086635	1			T1	1661		T2	463		T4	1
values[0x0]	147251	1			T1	102		T2	195		T4	7
values[0x1]	147787	1			T1	111		T2	213		T4	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	965358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1416315

1

T1

1102

T2

467

T4

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6818	1			T1	3		T2	3		T3	45
valid_sources[0x01]	6973	1			T1	7		T2	6		T3	30
valid_sources[0x02]	16128	1			T1	2		T2	5		T3	35
valid_sources[0x03]	6647	1			T1	7		T2	5		T3	33
valid_sources[0x04]	8206	1			T1	9		T2	8		T3	34
valid_sources[0x05]	6912	1			T1	4		T2	1		T3	32
valid_sources[0x06]	19523	1			T1	5		T2	2		T3	30
valid_sources[0x07]	11404	1			T1	10		T2	2		T3	49
valid_sources[0x08]	6982	1			T1	15		T2	5		T3	26
valid_sources[0x09]	7902	1			T1	6		T2	4		T3	40
valid_sources[0x0a]	9730	1			T1	8		T3	44		T7	2
valid_sources[0x0b]	8029	1			T1	1		T2	3		T3	34
valid_sources[0x0c]	7219	1			T1	3		T2	3		T3	24
valid_sources[0x0d]	7623	1			T2	1		T3	29		T10	4
valid_sources[0x0e]	12947	1			T1	6		T2	12		T3	29
valid_sources[0x0f]	6878	1			T1	9		T2	4		T3	38
valid_sources[0x10]	7725	1			T1	4		T2	4		T3	37
valid_sources[0x11]	11154	1			T1	7		T2	9		T3	32
valid_sources[0x12]	14234	1			T1	3		T2	8		T3	28
valid_sources[0x13]	10396	1			T1	11		T2	2		T4	1
valid_sources[0x14]	18106	1			T1	2		T2	1		T3	36
valid_sources[0x15]	7476	1			T1	8		T2	3		T3	29
valid_sources[0x16]	7254	1			T1	4		T2	5		T3	40
valid_sources[0x17]	7049	1			T1	9		T2	6		T3	26
valid_sources[0x18]	6941	1			T1	3		T2	3		T3	32
valid_sources[0x19]	8265	1			T2	4		T3	25		T7	3
valid_sources[0x1a]	8645	1			T1	2		T2	2		T3	41
valid_sources[0x1b]	7135	1			T1	5		T2	2		T3	30
valid_sources[0x1c]	7198	1			T1	1		T2	3		T3	41
valid_sources[0x1d]	7860	1			T1	6		T2	1		T3	45
valid_sources[0x1e]	7949	1			T1	17		T2	2		T3	34
valid_sources[0x1f]	8570	1			T1	4		T2	7		T3	34
valid_sources[0x20]	7063	1			T1	8		T2	8		T3	37
valid_sources[0x21]	7373	1			T1	3		T3	39		T10	1
valid_sources[0x22]	9693	1			T1	1		T3	33		T5	3
valid_sources[0x23]	7037	1			T1	10		T2	3		T3	27
valid_sources[0x24]	11165	1			T1	11		T2	5		T3	32
valid_sources[0x25]	11730	1			T1	7		T2	2		T3	41
valid_sources[0x26]	8878	1			T1	4		T2	4		T3	31
valid_sources[0x27]	11512	1			T1	10		T2	1		T3	33
valid_sources[0x28]	15491	1			T1	6		T2	3		T3	31
valid_sources[0x29]	7208	1			T1	9		T2	3		T3	37
valid_sources[0x2a]	9120	1			T1	3		T2	5		T3	37
valid_sources[0x2b]	7396	1			T1	13		T2	7		T3	29
valid_sources[0x2c]	7008	1			T1	1		T2	4		T3	31
valid_sources[0x2d]	8992	1			T1	9		T2	5		T3	30
valid_sources[0x2e]	7364	1			T1	7		T2	6		T3	23
valid_sources[0x2f]	9571	1			T1	6		T2	2		T3	28
valid_sources[0x30]	9432	1			T1	5		T2	2		T3	34
valid_sources[0x31]	8872	1			T1	1		T2	4		T3	36
valid_sources[0x32]	7066	1			T1	6		T2	9		T3	28
valid_sources[0x33]	6971	1			T1	4		T2	1		T3	43
valid_sources[0x34]	9399	1			T1	4		T2	3		T3	42
valid_sources[0x35]	7621	1			T1	20		T2	1		T3	29
valid_sources[0x36]	7011	1			T1	4		T2	4		T3	37
valid_sources[0x37]	7380	1			T1	9		T2	1		T3	33
valid_sources[0x38]	11302	1			T1	2		T2	8		T3	46
valid_sources[0x39]	7146	1			T1	2		T2	1		T3	40
valid_sources[0x3a]	12827	1			T1	3		T2	3		T3	31
valid_sources[0x3b]	7264	1			T1	8		T2	9		T3	35
valid_sources[0x3c]	12180	1			T1	9		T2	3		T3	37
valid_sources[0x3d]	9898	1			T1	17		T4	1		T3	37
valid_sources[0x3e]	11483	1			T1	11		T2	2		T3	30
valid_sources[0x3f]	7891	1			T1	21		T2	2		T3	25
valid_sources[0x40]	12772	1			T1	9		T2	3		T3	48
valid_sources[0x41]	8415	1			T1	10		T2	1		T3	31
valid_sources[0x42]	8015	1			T1	6		T2	3		T3	36
valid_sources[0x43]	8959	1			T1	5		T2	3		T3	26
valid_sources[0x44]	7278	1			T1	6		T2	3		T3	33
valid_sources[0x45]	10999	1			T1	5		T2	2		T3	30
valid_sources[0x46]	11030	1			T1	5		T2	6		T3	40
valid_sources[0x47]	8357	1			T1	8		T2	3		T3	27
valid_sources[0x48]	7858	1			T1	12		T2	1		T3	30
valid_sources[0x49]	7400	1			T1	7		T2	1		T3	28
valid_sources[0x4a]	6932	1			T1	3		T2	1		T3	38
valid_sources[0x4b]	6894	1			T1	3		T3	28		T5	2
valid_sources[0x4c]	14970	1			T1	7		T2	8		T3	25
valid_sources[0x4d]	7549	1			T1	10		T2	9		T3	44
valid_sources[0x4e]	9061	1			T1	4		T2	2		T3	25
valid_sources[0x4f]	7532	1			T1	4		T2	1		T3	31
valid_sources[0x50]	7064	1			T1	6		T2	3		T3	31
valid_sources[0x51]	6941	1			T1	4		T2	6		T3	35
valid_sources[0x52]	7448	1			T1	15		T3	33		T10	6
valid_sources[0x53]	11037	1			T1	1		T2	7		T3	25
valid_sources[0x54]	11167	1			T1	9		T2	1		T4	1
valid_sources[0x55]	7215	1			T1	5		T2	5		T3	26
valid_sources[0x56]	7478	1			T1	14		T2	5		T4	1
valid_sources[0x57]	12431	1			T1	2		T2	4		T3	24
valid_sources[0x58]	24465	1			T1	4		T2	2		T3	30
valid_sources[0x59]	12588	1			T1	8		T2	1		T3	33
valid_sources[0x5a]	6995	1			T1	8		T2	3		T3	39
valid_sources[0x5b]	6633	1			T1	4		T2	2		T3	35
valid_sources[0x5c]	7155	1			T1	7		T2	7		T3	34
valid_sources[0x5d]	6835	1			T1	3		T2	1		T3	31
valid_sources[0x5e]	6829	1			T1	6		T2	5		T3	37
valid_sources[0x5f]	7872	1			T1	3		T2	4		T3	37
valid_sources[0x60]	11235	1			T1	4		T2	3		T3	35
valid_sources[0x61]	7604	1			T1	26		T2	5		T3	31
valid_sources[0x62]	8843	1			T1	10		T2	5		T3	22
valid_sources[0x63]	25051	1			T1	8		T2	7		T3	25
valid_sources[0x64]	7654	1			T1	5		T2	3		T3	34
valid_sources[0x65]	9904	1			T1	4		T2	4		T3	36
valid_sources[0x66]	7048	1			T1	2		T2	8		T3	23
valid_sources[0x67]	8360	1			T1	6		T2	2		T3	29
valid_sources[0x68]	6911	1			T1	5		T2	5		T3	41
valid_sources[0x69]	7409	1			T1	7		T2	4		T3	53
valid_sources[0x6a]	7608	1			T1	6		T2	4		T3	31
valid_sources[0x6b]	11240	1			T1	4		T2	3		T3	30
valid_sources[0x6c]	11485	1			T1	14		T2	1		T3	42
valid_sources[0x6d]	7002	1			T1	14		T2	3		T3	37
valid_sources[0x6e]	19714	1			T1	8		T3	38		T10	3
valid_sources[0x6f]	7439	1			T1	6		T2	4		T3	40
valid_sources[0x70]	6859	1			T1	7		T2	3		T3	23
valid_sources[0x71]	10245	1			T1	9		T3	48		T5	1
valid_sources[0x72]	9157	1			T1	10		T2	1		T3	27
valid_sources[0x73]	7107	1			T1	6		T2	1		T3	35
valid_sources[0x74]	9865	1			T1	6		T2	3		T3	38
valid_sources[0x75]	7273	1			T1	20		T2	2		T3	41
valid_sources[0x76]	10867	1			T1	9		T2	2		T3	39
valid_sources[0x77]	7048	1			T1	3		T2	4		T4	1
valid_sources[0x78]	7304	1			T1	10		T2	4		T3	35
valid_sources[0x79]	12133	1			T1	7		T2	4		T3	39
valid_sources[0x7a]	8339	1			T1	23		T2	2		T3	36
valid_sources[0x7b]	7418	1			T1	7		T2	8		T3	31
valid_sources[0x7c]	7109	1			T1	5		T2	1		T3	46
valid_sources[0x7d]	6936	1			T1	6		T2	4		T3	43
valid_sources[0x7e]	19888	1			T1	10		T2	3		T3	50
valid_sources[0x7f]	6826	1			T1	11		T2	1		T4	1
valid_sources[0x80]	9945	1			T1	15		T2	3		T3	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1038841

1

T1

802

T2

218

T4

1

values[0x0]

all_enables

biggest_size

79824

1

T1

55

T2

101

T4

4

values[0x1]

all_enables

biggest_size

57572

1

T1

41

T2

74

T4

1