Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29076	1			T1	14		T3	26		T5	4
auto[PWRUP]	112	1			T44	2		T45	1		T64	3
auto[ONEST_0]	73	1			T64	2		T63	2		T206	1
auto[ONEST_021]	17	1			T64	1		T37	1		T211	1
auto[ONEST_1]	82	1			T6	2		T44	2		T64	1
auto[ONEST_DONE]	5	1			T212	1		T213	1		T214	1
auto[LP_0]	134	1			T6	1		T44	1		T63	3
auto[LP_021]	32	1			T6	1		T64	2		T108	1
auto[LP_1]	115	1			T44	2		T45	1		T63	1
auto[LP_EVAL]	68	1			T65	1		T37	3		T206	1
auto[LP_SLP]	496	1			T6	3		T44	7		T45	4
auto[LP_PWRUP]	26	1			T44	1		T65	1		T37	2
auto[NP_0]	148	1			T6	1		T44	1		T45	1
auto[NP_021]	42	1			T45	1		T64	1		T65	1
auto[NP_1]	167	1			T6	2		T44	4		T45	6
auto[NP_EVAL]	33	1			T44	1		T64	1		T68	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T65

1

T215

1

T105

1

min

28563

1

T1

14

T3

26

T5

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28573	1			T1	14		T3	26		T5	4
pow[0x1]	5	1			T216	1		T217	1		T218	1
pow[0x2]	14	1			T45	1		T65	1		T215	1
pow[0x3]	38	1			T44	2		T63	1		T65	2
pow[0x4]	55	1			T45	1		T64	1		T63	1
pow[0x5]	128	1			T6	1		T44	3		T45	1
pow[0x6]	234	1			T6	3		T45	1		T64	3
pow[0x7]	499	1			T6	9		T44	7		T45	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

186

1

T6

3

T44

2

T64

3

min

28090

1

T1

14

T3

26

T5

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28090	1			T1	14		T3	26		T5	4
pow[0x2]	1	1			T6	1		-	-		-	-
pow[0x3]	1	1			T32	1		-	-		-	-
pow[0x6]	1	1			T206	1		-	-		-	-
pow[0x7]	3	1			T211	1		T219	1		T220	1
pow[0x8]	3	1			T67	1		T221	1		T32	1
pow[0x9]	3	1			T222	1		T223	1		T224	1
pow[0xa]	14	1			T63	1		T225	1		T226	1
pow[0xb]	39	1			T44	1		T45	1		T37	1
pow[0xc]	75	1			T6	1		T45	2		T64	1
pow[0xd]	141	1			T6	1		T44	4		T45	4
pow[0xe]	283	1			T6	3		T44	5		T45	3
pow[0xf]	588	1			T6	6		T44	10		T45	6