Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2367	1			T2	9		T6	7		T14	4
auto[PWRUP]	124	1			T6	1		T44	2		T64	1
auto[ONEST_0]	77	1			T6	2		T44	2		T45	1
auto[ONEST_021]	22	1			T68	1		T206	1		T215	1
auto[ONEST_1]	76	1			T2	1		T6	1		T44	2
auto[ONEST_DONE]	4	1			T6	1		T343	1		T303	1
auto[LP_0]	136	1			T6	1		T44	2		T45	6
auto[LP_021]	39	1			T44	1		T63	1		T65	1
auto[LP_1]	144	1			T6	1		T45	2		T64	3
auto[LP_EVAL]	63	1			T6	1		T44	1		T45	2
auto[LP_SLP]	519	1			T2	1		T6	5		T44	7
auto[LP_PWRUP]	28	1			T63	2		T53	1		T212	1
auto[NP_0]	242	1			T6	2		T44	2		T45	1
auto[NP_021]	56	1			T344	2		T52	1		T53	3
auto[NP_1]	234	1			T2	1		T6	1		T44	1
auto[NP_EVAL]	43	1			T2	1		T44	1		T45	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T65

1

T222

1

T211

1

min

1958

1

T2

13

T6

6

T14

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1972	1			T2	13		T6	6		T14	4
pow[0x1]	9	1			T51	1		T215	1		T211	1
pow[0x2]	24	1			T51	1		T68	1		T215	1
pow[0x3]	40	1			T63	1		T37	1		T215	2
pow[0x4]	75	1			T44	4		T45	1		T344	1
pow[0x5]	128	1			T6	3		T44	2		T45	2
pow[0x6]	294	1			T6	3		T44	5		T45	8
pow[0x7]	549	1			T6	2		T44	7		T45	14

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

207

1

T6

2

T44

2

T45

3

min

1388

1

T2

11

T6

2

T14

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1397	1			T2	11		T6	2		T14	4
pow[0x1]	15	1			T51	1		T56	1		T105	1
pow[0x2]	31	1			T2	2		T52	2		T60	2
pow[0x3]	40	1			T53	1		T54	1		T57	1
pow[0x4]	54	1			T51	4		T53	1		T54	1
pow[0x5]	3	1			T44	1		T345	1		T346	1
pow[0x7]	1	1			T347	1		-	-		-	-
pow[0x8]	2	1			T221	1		T31	1		-	-
pow[0x9]	9	1			T64	1		T37	1		T206	1
pow[0xa]	18	1			T63	1		T56	1		T211	1
pow[0xb]	34	1			T45	1		T63	1		T65	2
pow[0xc]	66	1			T6	2		T44	1		T45	1
pow[0xd]	138	1			T44	4		T63	2		T65	1
pow[0xe]	318	1			T6	2		T44	5		T45	6
pow[0xf]	578	1			T6	5		T44	10		T45	14