Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1199170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1173223

1

T1

2644

T2

1449

T3

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2077289	1			T1	4825		T2	2523		T4	4067
values[0x0]	146856	1			T1	288		T2	166		T3	33
values[0x1]	148248	1			T1	300		T2	146		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	960343	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1412050

1

T1

3144

T2

1718

T3

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7522	1			T1	8		T2	15		T4	44
valid_sources[0x01]	11158	1			T1	5		T2	10		T4	25
valid_sources[0x02]	7964	1			T1	14		T2	10		T4	10
valid_sources[0x03]	20165	1			T1	11		T2	11		T4	13
valid_sources[0x04]	6988	1			T1	9		T2	9		T4	24
valid_sources[0x05]	6659	1			T1	14		T2	7		T5	18
valid_sources[0x06]	8291	1			T1	7		T2	6		T4	3
valid_sources[0x07]	6819	1			T1	5		T2	14		T4	7
valid_sources[0x08]	7657	1			T1	6		T2	14		T4	2
valid_sources[0x09]	7223	1			T1	10		T2	13		T4	84
valid_sources[0x0a]	6797	1			T1	14		T2	12		T4	15
valid_sources[0x0b]	8303	1			T1	9		T2	15		T4	46
valid_sources[0x0c]	6862	1			T1	8		T2	6		T5	33
valid_sources[0x0d]	7505	1			T1	14		T2	16		T4	14
valid_sources[0x0e]	6945	1			T1	8		T2	12		T4	31
valid_sources[0x0f]	8124	1			T1	10		T2	7		T4	31
valid_sources[0x10]	7001	1			T1	13		T2	6		T4	48
valid_sources[0x11]	6867	1			T1	14		T2	18		T5	56
valid_sources[0x12]	9371	1			T1	9		T2	11		T4	100
valid_sources[0x13]	9539	1			T1	9		T2	9		T5	46
valid_sources[0x14]	7896	1			T1	5		T2	6		T4	77
valid_sources[0x15]	7314	1			T1	14		T2	6		T4	64
valid_sources[0x16]	19773	1			T1	11		T2	5		T5	34
valid_sources[0x17]	7129	1			T1	9		T2	8		T4	18
valid_sources[0x18]	7773	1			T1	7		T2	10		T4	4
valid_sources[0x19]	6956	1			T1	6		T2	5		T5	18
valid_sources[0x1a]	8280	1			T1	16		T2	12		T4	38
valid_sources[0x1b]	12730	1			T1	249		T2	15		T4	21
valid_sources[0x1c]	8045	1			T1	18		T2	9		T4	39
valid_sources[0x1d]	7184	1			T1	10		T2	6		T4	49
valid_sources[0x1e]	7749	1			T1	11		T2	8		T5	31
valid_sources[0x1f]	11814	1			T1	362		T2	14		T4	15
valid_sources[0x20]	7663	1			T1	16		T2	6		T4	41
valid_sources[0x21]	19816	1			T1	10		T2	7		T4	27
valid_sources[0x22]	8155	1			T1	13		T2	9		T4	20
valid_sources[0x23]	9712	1			T1	8		T2	11		T4	4
valid_sources[0x24]	8751	1			T1	11		T2	16		T4	20
valid_sources[0x25]	10762	1			T1	13		T2	11		T4	4
valid_sources[0x26]	7637	1			T1	7		T2	5		T4	28
valid_sources[0x27]	6978	1			T1	16		T2	15		T4	25
valid_sources[0x28]	13374	1			T1	6		T2	13		T4	5
valid_sources[0x29]	13098	1			T1	269		T2	5		T4	19
valid_sources[0x2a]	6807	1			T1	11		T2	8		T4	1
valid_sources[0x2b]	8128	1			T1	23		T2	10		T4	10
valid_sources[0x2c]	6958	1			T1	12		T2	11		T4	3
valid_sources[0x2d]	6651	1			T1	14		T2	14		T5	30
valid_sources[0x2e]	7375	1			T1	11		T2	7		T4	5
valid_sources[0x2f]	7130	1			T1	14		T2	11		T4	45
valid_sources[0x30]	20183	1			T1	10		T2	12		T4	33
valid_sources[0x31]	6969	1			T1	9		T2	18		T4	12
valid_sources[0x32]	11377	1			T1	12		T2	15		T4	34
valid_sources[0x33]	15882	1			T1	13		T2	17		T4	14
valid_sources[0x34]	8684	1			T1	8		T2	9		T5	25
valid_sources[0x35]	7027	1			T1	8		T2	12		T4	51
valid_sources[0x36]	7047	1			T1	8		T2	9		T4	4
valid_sources[0x37]	7273	1			T1	8		T2	13		T5	34
valid_sources[0x38]	11070	1			T1	10		T2	21		T4	8
valid_sources[0x39]	12506	1			T1	8		T2	11		T4	17
valid_sources[0x3a]	7880	1			T1	9		T2	9		T4	32
valid_sources[0x3b]	11225	1			T1	10		T2	10		T4	21
valid_sources[0x3c]	6786	1			T1	12		T2	10		T4	30
valid_sources[0x3d]	7324	1			T1	14		T2	14		T4	2
valid_sources[0x3e]	6904	1			T1	8		T2	10		T5	50
valid_sources[0x3f]	7896	1			T1	7		T2	9		T5	40
valid_sources[0x40]	12057	1			T1	21		T2	10		T4	3
valid_sources[0x41]	11068	1			T1	20		T2	17		T4	56
valid_sources[0x42]	10977	1			T1	5		T2	14		T4	3
valid_sources[0x43]	9400	1			T1	22		T2	6		T5	29
valid_sources[0x44]	11267	1			T1	16		T2	8		T4	75
valid_sources[0x45]	7822	1			T1	13		T2	17		T4	33
valid_sources[0x46]	7642	1			T1	9		T2	13		T5	33
valid_sources[0x47]	32897	1			T1	12		T2	12		T4	6
valid_sources[0x48]	7952	1			T1	7		T2	11		T4	37
valid_sources[0x49]	7005	1			T1	16		T2	7		T4	28
valid_sources[0x4a]	8840	1			T1	6		T2	2		T4	6
valid_sources[0x4b]	18142	1			T1	13		T2	12		T4	8
valid_sources[0x4c]	7758	1			T1	113		T2	14		T4	2
valid_sources[0x4d]	8551	1			T1	6		T2	17		T4	12
valid_sources[0x4e]	7241	1			T1	9		T2	10		T4	6
valid_sources[0x4f]	7765	1			T1	13		T2	16		T4	14
valid_sources[0x50]	7936	1			T1	8		T2	13		T4	5
valid_sources[0x51]	11024	1			T1	12		T2	6		T4	5
valid_sources[0x52]	12000	1			T1	11		T2	12		T4	28
valid_sources[0x53]	6708	1			T1	7		T2	13		T3	55
valid_sources[0x54]	7928	1			T1	119		T2	7		T5	21
valid_sources[0x55]	8108	1			T1	7		T2	16		T4	13
valid_sources[0x56]	13571	1			T1	9		T2	10		T4	26
valid_sources[0x57]	6939	1			T1	13		T2	23		T5	46
valid_sources[0x58]	8475	1			T1	11		T2	17		T4	4
valid_sources[0x59]	8219	1			T1	5		T2	7		T4	32
valid_sources[0x5a]	6804	1			T1	9		T2	19		T5	11
valid_sources[0x5b]	11585	1			T1	7		T2	15		T4	63
valid_sources[0x5c]	7020	1			T1	12		T2	7		T5	36
valid_sources[0x5d]	21848	1			T1	10		T2	9		T4	7
valid_sources[0x5e]	7322	1			T1	271		T2	4		T5	45
valid_sources[0x5f]	7077	1			T1	6		T2	11		T5	34
valid_sources[0x60]	7225	1			T1	9		T2	7		T4	21
valid_sources[0x61]	6473	1			T1	10		T2	7		T5	20
valid_sources[0x62]	11422	1			T1	144		T2	16		T4	23
valid_sources[0x63]	9392	1			T1	5		T2	12		T5	61
valid_sources[0x64]	7097	1			T1	15		T2	10		T4	18
valid_sources[0x65]	13105	1			T1	19		T2	11		T4	6
valid_sources[0x66]	9158	1			T1	6		T2	20		T4	10
valid_sources[0x67]	6831	1			T1	6		T2	16		T4	6
valid_sources[0x68]	8988	1			T1	5		T2	13		T4	11
valid_sources[0x69]	8400	1			T1	16		T2	12		T5	18
valid_sources[0x6a]	7371	1			T1	14		T2	14		T4	23
valid_sources[0x6b]	7499	1			T1	10		T2	9		T5	14
valid_sources[0x6c]	7811	1			T1	9		T2	14		T4	4
valid_sources[0x6d]	7046	1			T1	14		T2	11		T4	4
valid_sources[0x6e]	8296	1			T1	7		T2	7		T4	1
valid_sources[0x6f]	7796	1			T1	40		T2	7		T4	3
valid_sources[0x70]	17294	1			T1	5		T2	11		T4	60
valid_sources[0x71]	16387	1			T1	18		T2	9		T4	42
valid_sources[0x72]	6880	1			T1	10		T2	8		T4	25
valid_sources[0x73]	15968	1			T1	13		T2	13		T4	24
valid_sources[0x74]	7802	1			T1	5		T2	11		T5	45
valid_sources[0x75]	7127	1			T1	21		T2	9		T5	43
valid_sources[0x76]	9610	1			T1	10		T2	15		T4	21
valid_sources[0x77]	8837	1			T1	17		T2	13		T5	42
valid_sources[0x78]	11149	1			T1	11		T2	8		T4	3
valid_sources[0x79]	10357	1			T1	11		T2	14		T4	49
valid_sources[0x7a]	6693	1			T1	61		T2	6		T4	19
valid_sources[0x7b]	6901	1			T1	10		T2	12		T4	2
valid_sources[0x7c]	12467	1			T1	6		T2	9		T5	24
valid_sources[0x7d]	9650	1			T1	15		T2	7		T5	38
valid_sources[0x7e]	22124	1			T1	87		T2	9		T4	18
valid_sources[0x7f]	6971	1			T1	15		T2	17		T4	38
valid_sources[0x80]	12104	1			T1	9		T2	16		T4	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1037043

1

T1

2411

T2

1289

T4

2043

values[0x0]

all_enables

biggest_size

79499

1

T1

149

T2

95

T3

20

values[0x1]

all_enables

biggest_size

56681

1

T1

84

T2

65

T3

15