Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31740	1			T1	24		T2	25		T4	6
auto[PWRUP]	108	1			T8	3		T41	2		T27	3
auto[ONEST_0]	81	1			T8	2		T53	2		T54	1
auto[ONEST_021]	21	1			T8	2		T57	2		T54	1
auto[ONEST_1]	79	1			T8	2		T27	1		T53	2
auto[ONEST_DONE]	7	1			T226	1		T227	1		T228	1
auto[LP_0]	167	1			T8	3		T41	2		T27	2
auto[LP_021]	30	1			T54	1		T229	1		T34	2
auto[LP_1]	124	1			T8	3		T41	1		T27	2
auto[LP_EVAL]	78	1			T8	6		T41	2		T53	4
auto[LP_SLP]	517	1			T8	7		T41	5		T27	10
auto[LP_PWRUP]	24	1			T27	1		T57	2		T43	1
auto[NP_0]	137	1			T41	5		T27	1		T53	2
auto[NP_021]	34	1			T41	3		T53	1		T57	2
auto[NP_1]	158	1			T41	3		T27	2		T57	2
auto[NP_EVAL]	39	1			T41	1		T27	1		T57	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T27

1

T53

1

T34

1

min

31155

1

T1

24

T2

25

T4

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31157	1			T1	24		T2	25		T4	6
pow[0x1]	8	1			T230	1		T231	1		T232	1
pow[0x2]	22	1			T27	1		T53	1		T54	1
pow[0x3]	35	1			T41	1		T53	2		T57	1
pow[0x4]	73	1			T27	1		T53	1		T229	2
pow[0x5]	145	1			T8	4		T41	3		T53	3
pow[0x6]	260	1			T8	6		T41	3		T27	4
pow[0x7]	530	1			T8	8		T41	7		T27	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

225

1

T8

2

T41

1

T27

2

min

30655

1

T1

24

T2

25

T4

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30655	1			T1	24		T2	25		T4	6
pow[0x5]	2	1			T47	1		T233	1		-	-
pow[0x6]	1	1			T228	1		-	-		-	-
pow[0x7]	4	1			T226	1		T234	1		T235	1
pow[0x8]	5	1			T8	1		T45	1		T56	1
pow[0x9]	10	1			T8	1		T36	2		T47	1
pow[0xa]	22	1			T53	1		T43	1		T55	1
pow[0xb]	38	1			T8	1		T41	1		T53	1
pow[0xc]	55	1			T41	1		T27	1		T53	1
pow[0xd]	157	1			T8	3		T27	3		T53	5
pow[0xe]	291	1			T8	6		T41	1		T27	4
pow[0xf]	611	1			T8	14		T41	7		T27	9