Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2387	1			T8	17		T41	17		T14	15
auto[PWRUP]	146	1			T8	2		T41	1		T27	5
auto[ONEST_0]	84	1			T8	1		T41	1		T54	1
auto[ONEST_021]	22	1			T8	2		T53	1		T357	1
auto[ONEST_1]	77	1			T41	2		T27	1		T53	2
auto[ONEST_DONE]	6	1			T8	1		T242	1		T260	1
auto[LP_0]	119	1			T41	1		T53	2		T54	2
auto[LP_021]	26	1			T8	1		T41	1		T185	1
auto[LP_1]	134	1			T8	1		T41	3		T27	3
auto[LP_EVAL]	61	1			T57	2		T229	2		T15	2
auto[LP_SLP]	560	1			T8	7		T41	5		T14	1
auto[LP_PWRUP]	27	1			T41	1		T53	1		T42	1
auto[NP_0]	235	1			T8	1		T41	5		T14	3
auto[NP_021]	48	1			T41	1		T27	1		T57	1
auto[NP_1]	238	1			T8	3		T41	2		T14	3
auto[NP_EVAL]	35	1			T8	1		T41	1		T54	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T41

1

T358

1

T359

1

min

2023

1

T8

9

T41

7

T14

22

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2038	1			T8	9		T41	7		T14	22
pow[0x1]	12	1			T41	1		T15	1		T232	1
pow[0x2]	23	1			T53	2		T54	1		T42	1
pow[0x3]	48	1			T53	2		T15	1		T42	1
pow[0x4]	56	1			T41	3		T53	1		T57	1
pow[0x5]	132	1			T8	2		T41	3		T27	3
pow[0x6]	270	1			T8	3		T41	3		T27	4
pow[0x7]	528	1			T8	5		T41	9		T27	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

212

1

T41

4

T27

3

T53

5

min

1437

1

T8

2

T41

3

T14

16

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1443	1			T8	2		T41	3		T14	17
pow[0x1]	12	1			T39	4		T15	2		T360	1
pow[0x2]	24	1			T14	2		T40	1		T45	1
pow[0x3]	50	1			T14	3		T42	1		T43	1
pow[0x4]	55	1			T40	1		T15	1		T42	1
pow[0x6]	2	1			T361	1		T362	1		-	-
pow[0x7]	5	1			T232	1		T242	1		T363	1
pow[0x8]	2	1			T53	1		T56	1		-	-
pow[0x9]	10	1			T8	1		T53	1		T364	1
pow[0xa]	13	1			T8	1		T55	1		T47	1
pow[0xb]	45	1			T8	2		T53	1		T57	1
pow[0xc]	69	1			T41	1		T27	2		T53	1
pow[0xd]	151	1			T8	1		T41	1		T27	2
pow[0xe]	343	1			T8	4		T41	8		T27	3
pow[0xf]	600	1			T8	8		T41	11		T27	8