Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1181112	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1153023

1

T1

540

T2

946

T3

2622

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2042454	1			T2	1648		T3	4867		T4	836
values[0x0]	145493	1			T1	680		T2	108		T3	241
values[0x1]	146188	1			T1	613		T2	103		T3	289

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	946438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1387697

1

T1

618

T2

1147

T3

3170

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7780	1			T1	3		T3	4		T4	5
valid_sources[0x01]	11024	1			T1	4		T3	4		T4	2
valid_sources[0x02]	6547	1			T1	6		T3	9		T4	6
valid_sources[0x03]	7756	1			T1	7		T2	9		T3	6
valid_sources[0x04]	7852	1			T1	6		T2	28		T3	8
valid_sources[0x05]	11380	1			T1	7		T2	4		T3	7
valid_sources[0x06]	10620	1			T1	8		T2	2		T3	4
valid_sources[0x07]	9797	1			T1	5		T4	2		T6	2
valid_sources[0x08]	6845	1			T1	5		T4	2		T5	1
valid_sources[0x09]	6456	1			T1	6		T2	2		T3	1
valid_sources[0x0a]	6586	1			T1	3		T3	2		T4	1
valid_sources[0x0b]	7199	1			T1	5		T2	4		T3	12
valid_sources[0x0c]	10852	1			T1	5		T2	1		T3	3
valid_sources[0x0d]	9511	1			T1	4		T2	1		T3	5
valid_sources[0x0e]	12646	1			T1	2		T2	1		T3	32
valid_sources[0x0f]	7386	1			T1	5		T3	3		T4	2
valid_sources[0x10]	6935	1			T1	5		T4	2		T6	1
valid_sources[0x11]	7270	1			T1	6		T3	6		T5	3
valid_sources[0x12]	6847	1			T1	5		T2	12		T3	6
valid_sources[0x13]	7140	1			T1	5		T2	3		T3	2
valid_sources[0x14]	7048	1			T1	3		T2	3		T3	3
valid_sources[0x15]	17412	1			T1	6		T3	3		T4	2
valid_sources[0x16]	11455	1			T1	5		T2	10		T4	3
valid_sources[0x17]	10672	1			T1	3		T4	7		T5	156
valid_sources[0x18]	7709	1			T1	5		T2	11		T4	3
valid_sources[0x19]	11039	1			T1	6		T2	15		T3	1
valid_sources[0x1a]	7153	1			T1	7		T2	9		T3	4
valid_sources[0x1b]	12689	1			T1	5		T3	8		T4	6
valid_sources[0x1c]	6553	1			T1	6		T2	6		T3	15
valid_sources[0x1d]	6635	1			T1	4		T2	9		T3	9
valid_sources[0x1e]	7614	1			T1	2		T4	2		T5	5
valid_sources[0x1f]	13309	1			T1	8		T3	11		T4	3
valid_sources[0x20]	15241	1			T1	5		T2	7		T3	15
valid_sources[0x21]	10798	1			T1	7		T2	6		T3	3
valid_sources[0x22]	7108	1			T1	2		T2	7		T4	1
valid_sources[0x23]	6236	1			T1	4		T2	2		T3	14
valid_sources[0x24]	6819	1			T1	2		T2	36		T4	3
valid_sources[0x25]	6614	1			T1	5		T2	26		T4	1
valid_sources[0x26]	9226	1			T1	7		T2	7		T3	1
valid_sources[0x27]	6452	1			T1	6		T4	3		T5	3
valid_sources[0x28]	17505	1			T1	3		T2	13		T3	6
valid_sources[0x29]	6457	1			T1	6		T5	25		T6	6
valid_sources[0x2a]	6532	1			T1	7		T2	12		T4	1
valid_sources[0x2b]	7541	1			T1	4		T2	26		T3	1
valid_sources[0x2c]	12461	1			T1	6		T2	11		T3	11
valid_sources[0x2d]	7679	1			T1	3		T2	24		T4	5
valid_sources[0x2e]	6710	1			T1	4		T2	17		T5	4
valid_sources[0x2f]	11963	1			T1	3		T2	5		T4	3
valid_sources[0x30]	16353	1			T1	3		T2	1		T4	5
valid_sources[0x31]	11141	1			T1	6		T2	12		T5	110
valid_sources[0x32]	7300	1			T1	5		T4	5		T6	1
valid_sources[0x33]	13585	1			T1	4		T2	2		T4	7
valid_sources[0x34]	7424	1			T1	5		T3	4		T4	10
valid_sources[0x35]	6790	1			T1	8		T2	4		T3	4
valid_sources[0x36]	13041	1			T1	7		T2	13		T4	2
valid_sources[0x37]	8705	1			T1	4		T2	18		T3	2
valid_sources[0x38]	6959	1			T1	6		T2	2		T3	1
valid_sources[0x39]	6815	1			T1	3		T2	18		T3	3
valid_sources[0x3a]	6410	1			T1	7		T2	7		T3	12
valid_sources[0x3b]	6506	1			T1	3		T4	2		T5	10
valid_sources[0x3c]	11420	1			T1	6		T4	1		T5	4
valid_sources[0x3d]	7307	1			T1	6		T3	3		T6	2
valid_sources[0x3e]	7037	1			T1	2		T2	12		T3	3
valid_sources[0x3f]	7674	1			T1	8		T4	6		T5	62
valid_sources[0x40]	6584	1			T1	5		T2	16		T3	6
valid_sources[0x41]	9011	1			T1	4		T2	8		T3	4
valid_sources[0x42]	11092	1			T1	4		T2	3		T3	3
valid_sources[0x43]	9128	1			T1	5		T2	8		T3	5
valid_sources[0x44]	6897	1			T1	5		T2	17		T5	5
valid_sources[0x45]	7499	1			T1	8		T2	12		T3	2
valid_sources[0x46]	7824	1			T1	5		T2	32		T3	21
valid_sources[0x47]	8333	1			T1	7		T2	5		T3	1
valid_sources[0x48]	11528	1			T1	4		T3	5		T4	2
valid_sources[0x49]	7504	1			T1	4		T2	2		T3	13
valid_sources[0x4a]	7216	1			T1	1		T4	7		T5	4
valid_sources[0x4b]	6579	1			T1	7		T2	17		T3	7
valid_sources[0x4c]	6670	1			T1	7		T2	2		T4	3
valid_sources[0x4d]	7292	1			T1	5		T2	8		T4	1
valid_sources[0x4e]	6608	1			T1	6		T2	15		T5	3
valid_sources[0x4f]	6254	1			T1	5		T2	23		T3	7
valid_sources[0x50]	11279	1			T1	1		T2	8		T3	33
valid_sources[0x51]	13740	1			T1	5		T3	2		T4	1
valid_sources[0x52]	10553	1			T1	8		T2	5		T5	13
valid_sources[0x53]	6828	1			T1	2		T4	10		T5	8
valid_sources[0x54]	9512	1			T1	5		T2	2		T4	1
valid_sources[0x55]	6976	1			T1	9		T3	2		T4	6
valid_sources[0x56]	9820	1			T1	3		T2	13		T4	4
valid_sources[0x57]	6627	1			T1	5		T2	24		T3	4
valid_sources[0x58]	6878	1			T1	6		T3	21		T4	3
valid_sources[0x59]	6533	1			T1	7		T3	6		T4	6
valid_sources[0x5a]	8000	1			T1	4		T2	10		T3	1
valid_sources[0x5b]	6850	1			T1	3		T2	1		T4	1
valid_sources[0x5c]	6579	1			T1	8		T2	7		T3	2
valid_sources[0x5d]	7938	1			T1	3		T2	11		T4	15
valid_sources[0x5e]	6485	1			T1	7		T4	4		T5	13
valid_sources[0x5f]	11288	1			T1	7		T3	4		T4	3
valid_sources[0x60]	8791	1			T1	6		T2	1		T3	9
valid_sources[0x61]	11920	1			T1	6		T2	10		T3	15
valid_sources[0x62]	10455	1			T1	4		T3	9		T4	4
valid_sources[0x63]	12139	1			T1	7		T2	16		T3	25
valid_sources[0x64]	6311	1			T1	3		T2	4		T3	9
valid_sources[0x65]	7254	1			T1	3		T3	30		T5	2
valid_sources[0x66]	6587	1			T1	7		T2	17		T4	4
valid_sources[0x67]	7926	1			T1	5		T2	1		T3	11
valid_sources[0x68]	6594	1			T1	7		T2	7		T3	6
valid_sources[0x69]	10936	1			T1	5		T2	12		T3	3
valid_sources[0x6a]	12971	1			T1	4		T2	31		T4	15
valid_sources[0x6b]	7087	1			T1	6		T2	10		T3	2
valid_sources[0x6c]	7003	1			T1	9		T3	1		T4	13
valid_sources[0x6d]	6659	1			T1	1		T2	41		T3	1
valid_sources[0x6e]	7081	1			T1	7		T4	2		T5	9
valid_sources[0x6f]	7700	1			T1	5		T4	1		T7	2
valid_sources[0x70]	6683	1			T1	5		T2	29		T4	12
valid_sources[0x71]	10464	1			T1	5		T2	1		T4	3
valid_sources[0x72]	6792	1			T1	5		T2	7		T3	20
valid_sources[0x73]	7623	1			T1	4		T2	13		T4	4
valid_sources[0x74]	6738	1			T1	7		T2	5		T3	11
valid_sources[0x75]	11390	1			T1	5		T3	1		T4	4
valid_sources[0x76]	7038	1			T1	5		T2	8		T3	11
valid_sources[0x77]	6496	1			T1	8		T2	9		T3	15
valid_sources[0x78]	19116	1			T1	1		T4	7		T5	14
valid_sources[0x79]	8214	1			T1	2		T3	4		T4	15
valid_sources[0x7a]	7743	1			T1	3		T3	3		T4	2
valid_sources[0x7b]	6655	1			T1	12		T2	5		T4	7
valid_sources[0x7c]	6647	1			T1	2		T2	28		T4	4
valid_sources[0x7d]	11686	1			T1	5		T2	2		T3	20
valid_sources[0x7e]	6728	1			T1	5		T2	6		T3	7
valid_sources[0x7f]	10449	1			T1	5		T3	1		T4	1
valid_sources[0x80]	7349	1			T1	3		T2	2		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1017848

1

T2

834

T3

2415

T4

403

values[0x0]

all_enables

biggest_size

78908

1

T1

331

T2

71

T3

118

values[0x1]

all_enables

biggest_size

56267

1

T1

209

T2

41

T3

89