Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
84.44	84.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	84.44	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	7	38	84.44

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30227	1			T1	328		T2	19		T3	11
auto[PWRUP]	101	1			T1	4		T51	3		T52	1
auto[ONEST_0]	83	1			T1	4		T36	1		T30	1
auto[ONEST_021]	29	1			T1	1		T36	1		T52	1
auto[ONEST_1]	94	1			T1	1		T36	1		T30	1
auto[ONEST_DONE]	5	1			T202	1		T203	1		T204	2
auto[LP_0]	133	1			T1	4		T36	1		T30	4
auto[LP_021]	37	1			T1	1		T38	2		T205	1
auto[LP_1]	144	1			T1	2		T51	1		T52	3
auto[LP_EVAL]	58	1			T51	1		T52	1		T38	1
auto[LP_SLP]	503	1			T1	9		T36	2		T30	7
auto[LP_PWRUP]	30	1			T35	1		T205	1		T206	3
auto[NP_0]	152	1			T1	1		T36	1		T30	1
auto[NP_021]	34	1			T15	1		T52	2		T205	1
auto[NP_1]	149	1			T1	1		T35	1		T36	1
auto[NP_EVAL]	30	1			T52	3		T205	2		T206	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T36

1

T207

1

T208

1

min

29713

1

T1

323

T2

19

T3

11

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29720	1			T1	323		T2	19		T3	11
pow[0x1]	9	1			T136	1		T208	1		T209	1
pow[0x2]	15	1			T38	1		T210	1		T18	1
pow[0x3]	29	1			T35	1		T30	2		T52	2
pow[0x4]	66	1			T1	2		T30	1		T52	2
pow[0x5]	124	1			T1	3		T35	1		T36	1
pow[0x6]	280	1			T1	7		T36	1		T30	7
pow[0x7]	523	1			T1	7		T36	1		T15	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

203

1

T1

6

T30

2

T51

2

min

29211

1

T1

311

T2

19

T3

11

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1
pow[0x8]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29211	1			T1	311		T2	19		T3	11
pow[0x3]	2	1			T211	1		T203	1		-	-
pow[0x7]	2	1			T38	1		T212	1		-	-
pow[0x9]	10	1			T38	1		T136	1		T212	1
pow[0xa]	24	1			T30	1		T52	1		T212	1
pow[0xb]	36	1			T52	1		T38	2		T205	1
pow[0xc]	60	1			T1	1		T36	1		T30	2
pow[0xd]	159	1			T1	5		T36	1		T30	3
pow[0xe]	261	1			T1	2		T36	1		T30	3
pow[0xf]	616	1			T1	16		T36	1		T30	6