Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2341	1			T1	18		T3	4		T49	2
auto[PWRUP]	157	1			T1	1		T29	1		T30	3
auto[ONEST_0]	70	1			T1	1		T36	1		T51	2
auto[ONEST_021]	20	1			T30	1		T51	1		T38	1
auto[ONEST_1]	79	1			T1	2		T35	1		T36	1
auto[ONEST_DONE]	6	1			T342	1		T343	1		T344	1
auto[LP_0]	113	1			T1	1		T35	1		T51	1
auto[LP_021]	29	1			T1	1		T35	1		T52	1
auto[LP_1]	160	1			T1	3		T36	1		T30	2
auto[LP_EVAL]	67	1			T1	1		T35	1		T51	1
auto[LP_SLP]	524	1			T1	6		T35	2		T36	2
auto[LP_PWRUP]	36	1			T1	1		T36	1		T30	1
auto[NP_0]	203	1			T1	1		T36	6		T15	2
auto[NP_021]	77	1			T1	1		T36	2		T29	2
auto[NP_1]	249	1			T1	4		T35	2		T36	3
auto[NP_EVAL]	34	1			T36	1		T52	2		T38	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T51

1

T52

1

T345

1

min

2021

1

T1

9

T3

4

T49

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2039	1			T1	9		T3	4		T49	2
pow[0x1]	11	1			T345	1		T19	1		T20	1
pow[0x2]	26	1			T52	1		T38	1		T136	1
pow[0x3]	34	1			T36	1		T52	1		T38	2
pow[0x4]	71	1			T1	1		T36	1		T30	1
pow[0x5]	143	1			T1	2		T35	1		T30	4
pow[0x6]	275	1			T1	6		T35	1		T36	3
pow[0x7]	519	1			T1	8		T36	4		T15	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

196

1

T1

1

T36

2

T15

1

min

1440

1

T1

3

T3

4

T49

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1445	1			T1	3		T3	4		T49	2
pow[0x1]	23	1			T40	1		T46	1		T18	1
pow[0x2]	33	1			T35	1		T38	1		T40	5
pow[0x3]	55	1			T36	2		T16	1		T17	2
pow[0x4]	55	1			T36	5		T15	3		T29	4
pow[0x5]	3	1			T136	1		T346	1		T347	1
pow[0x6]	4	1			T348	1		T349	1		T301	1
pow[0x7]	2	1			T350	1		T351	1		-	-
pow[0x8]	6	1			T36	1		T52	1		T352	1
pow[0x9]	11	1			T52	1		T206	1		T212	1
pow[0xa]	21	1			T52	1		T205	1		T212	1
pow[0xb]	36	1			T30	1		T38	2		T207	1
pow[0xc]	62	1			T52	1		T38	1		T205	1
pow[0xd]	146	1			T36	1		T30	4		T51	5
pow[0xe]	297	1			T1	7		T36	1		T30	2
pow[0xf]	576	1			T1	14		T35	2		T36	4