Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T10

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T8
0	1	Covered	T3,T5,T8
1	0	Covered	T3,T5,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T11
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T3,T6,T11
1	0	Covered	T3,T6,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T8
0	1	Covered	T3,T4,T8
1	0	Covered	T3,T4,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T5,T11,T12
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T12
0	1	Covered	T5,T12,T13
1	0	Covered	T5,T11,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T11
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T11
0	1	Covered	T3,T5,T11
1	0	Covered	T3,T5,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T11
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T3,T6,T11
1	0	Covered	T3,T6,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T8
0	1	Covered	T3,T4,T8
1	0	Covered	T3,T4,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T5,T11,T12
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T11,T12
0	1	Covered	T5,T11,T12
1	0	Covered	T5,T11,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T2,T3,T5
1	1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T2,T3,T5
1	1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T2,T3,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T11,T12
1	0	Covered	T8,T11,T12

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T12,T15
1	0	Covered	T8,T11,T12

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T12
1	0	Covered	T11,T13,T48
1	1	Covered	T8,T12,T13

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T10
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T11,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T11,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	36142292	35823930	0	0
gen_filter_match[0].MatchCheck00_A	36142292	12138054	0	0
gen_filter_match[0].MatchCheck01_A	36142292	2573895	0	0
gen_filter_match[0].MatchCheck10_A	36142292	2941832	0	0
gen_filter_match[0].MatchCheck11_A	36142292	18170149	0	0
gen_filter_match[1].MatchCheck00_A	36142292	13510729	0	0
gen_filter_match[1].MatchCheck01_A	36142292	1159710	0	0
gen_filter_match[1].MatchCheck10_A	36142292	1137939	0	0
gen_filter_match[1].MatchCheck11_A	36142292	20015552	0	0
gen_filter_match[2].MatchCheck00_A	36142292	12155493	0	0
gen_filter_match[2].MatchCheck01_A	36142292	655900	0	0
gen_filter_match[2].MatchCheck10_A	36142292	469217	0	0
gen_filter_match[2].MatchCheck11_A	36142292	22543320	0	0
gen_filter_match[3].MatchCheck00_A	36142292	14214184	0	0
gen_filter_match[3].MatchCheck01_A	36142292	361986	0	0
gen_filter_match[3].MatchCheck10_A	36142292	400362	0	0
gen_filter_match[3].MatchCheck11_A	36142292	20847398	0	0
gen_filter_match[4].MatchCheck00_A	36142292	13689307	0	0
gen_filter_match[4].MatchCheck01_A	36142292	70624	0	0
gen_filter_match[4].MatchCheck10_A	36142292	110	0	0
gen_filter_match[4].MatchCheck11_A	36142292	22063889	0	0
gen_filter_match[5].MatchCheck00_A	36142292	14608919	0	0
gen_filter_match[5].MatchCheck01_A	36142292	33408	0	0
gen_filter_match[5].MatchCheck10_A	36142292	74964	0	0
gen_filter_match[5].MatchCheck11_A	36142292	21106639	0	0
gen_filter_match[6].MatchCheck00_A	36142292	14584353	0	0
gen_filter_match[6].MatchCheck01_A	36142292	99078	0	0
gen_filter_match[6].MatchCheck10_A	36142292	121	0	0
gen_filter_match[6].MatchCheck11_A	36142292	21140378	0	0
gen_filter_match[7].MatchCheck00_A	36142292	15164162	0	0
gen_filter_match[7].MatchCheck01_A	36142292	235411	0	0
gen_filter_match[7].MatchCheck10_A	36142292	164979	0	0
gen_filter_match[7].MatchCheck11_A	36142292	20259378	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	35823930	0	0
T1	24086	21014	0	0
T2	64549	64457	0	0
T3	66954	66638	0	0
T4	32714	32652	0	0
T5	96142	96070	0	0
T6	64641	64580	0	0
T7	8785	8697	0	0
T8	72313	72246	0	0
T9	8962	8886	0	0
T14	101	18	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	12138054	0	0
T1	24086	20128	0	0
T2	64549	4	0	0
T3	66954	35034	0	0
T4	32714	4	0	0
T5	96142	64523	0	0
T6	64641	32162	0	0
T7	8785	8697	0	0
T8	72313	33407	0	0
T9	8962	8886	0	0
T14	101	18	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	2573895	0	0
T5	96142	31547	0	0
T6	64641	0	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	0	0	0
T12	82091	0	0	0
T13	0	35726	0	0
T14	101	0	0	0
T15	0	1463	0	0
T32	0	37037	0	0
T36	0	32358	0	0
T48	0	53812	0	0
T49	9372	0	0	0
T134	0	31293	0	0
T135	0	33343	0	0
T136	0	34976	0	0
T137	0	33897	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	2941832	0	0
T6	64641	32418	0	0
T7	8785	0	0	0
T8	72313	38839	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	0	0	0
T12	82091	50326	0	0
T13	106216	0	0	0
T14	101	0	0	0
T26	0	64980	0	0
T27	0	33958	0	0
T31	0	31717	0	0
T38	0	13	0	0
T49	9372	0	0	0
T50	0	2	0	0
T90	0	1	0	0
T135	0	33562	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	18170149	0	0
T1	24086	886	0	0
T2	64549	64453	0	0
T3	66954	31604	0	0
T4	32714	32648	0	0
T5	96142	0	0	0
T6	64641	0	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T11	0	37135	0	0
T12	0	31679	0	0
T13	0	38039	0	0
T14	101	0	0	0
T37	0	31819	0	0
T48	0	42437	0	0
T50	0	32684	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	13510729	0	0
T1	24086	21014	0	0
T2	64549	4	0	0
T3	66954	35034	0	0
T4	32714	4	0	0
T5	96142	32179	0	0
T6	64641	32422	0	0
T7	8785	8697	0	0
T8	72313	4	0	0
T9	8962	8886	0	0
T14	101	18	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	1159710	0	0
T8	72313	33403	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	0	0	0
T12	82091	0	0	0
T13	106216	32348	0	0
T14	101	0	0	0
T15	0	3190	0	0
T27	0	32433	0	0
T36	0	18914	0	0
T37	64513	0	0	0
T49	9372	0	0	0
T50	32753	0	0	0
T138	0	34076	0	0
T139	0	36509	0	0
T140	0	34945	0	0
T141	0	40658	0	0
T142	0	31492	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	1137939	0	0
T5	96142	1	0	0
T6	64641	32158	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	0	0	0
T12	82091	0	0	0
T14	101	0	0	0
T36	0	1	0	0
T44	0	51695	0	0
T49	9372	0	0	0
T50	0	2	0	0
T138	0	1	0	0
T140	0	37152	0	0
T142	0	32839	0	0
T143	0	1	0	0
T144	0	2	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	20015552	0	0
T2	64549	64453	0	0
T3	66954	31604	0	0
T4	32714	32648	0	0
T5	96142	63890	0	0
T6	64641	0	0	0
T7	8785	0	0	0
T8	72313	38839	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	0	69514	0	0
T12	0	50326	0	0
T14	101	0	0	0
T37	0	31819	0	0
T47	0	32625	0	0
T50	0	32684	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	12155493	0	0
T1	24086	21014	0	0
T2	64549	4	0	0
T3	66954	2255	0	0
T4	32714	32652	0	0
T5	96142	63726	0	0
T6	64641	32422	0	0
T7	8785	8697	0	0
T8	72313	33407	0	0
T9	8962	8886	0	0
T14	101	18	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	655900	0	0
T13	106216	38039	0	0
T34	0	32831	0	0
T35	18644	0	0	0
T37	64513	0	0	0
T41	690	0	0	0
T42	64415	0	0	0
T47	97832	0	0	0
T48	96312	0	0	0
T50	32753	0	0	0
T110	33970	0	0	0
T111	690	0	0	0
T145	0	34255	0	0
T146	0	35623	0	0
T147	0	1	0	0
T148	0	32846	0	0
T149	0	1	0	0
T150	0	32840	0	0
T151	0	2	0	0
T152	0	34714	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	469217	0	0
T5	96142	1	0	0
T6	64641	1	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	37135	0	0
T12	82091	0	0	0
T14	101	0	0	0
T26	0	1	0	0
T36	0	4	0	0
T38	0	10852	0	0
T48	0	42437	0	0
T49	9372	0	0	0
T50	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	22543320	0	0
T2	64549	64453	0	0
T3	66954	64383	0	0
T4	32714	0	0	0
T5	96142	32343	0	0
T6	64641	32157	0	0
T7	8785	0	0	0
T8	72313	38839	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	0	32379	0	0
T13	0	32348	0	0
T14	101	0	0	0
T37	0	31819	0	0
T47	0	97768	0	0
T50	0	32684	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	14214184	0	0
T1	24086	21014	0	0
T2	64549	4	0	0
T3	66954	2255	0	0
T4	32714	4	0	0
T5	96142	31551	0	0
T6	64641	32161	0	0
T7	8785	8697	0	0
T8	72313	38843	0	0
T9	8962	8886	0	0
T14	101	18	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	361986	0	0
T6	64641	1	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	0	0	0
T12	82091	0	0	0
T13	106216	0	0	0
T14	101	0	0	0
T20	0	1946	0	0
T49	9372	0	0	0
T81	0	1	0	0
T86	0	1	0	0
T97	0	36464	0	0
T141	0	2	0	0
T147	0	1	0	0
T153	0	1	0	0
T155	0	34103	0	0
T156	0	32779	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	400362	0	0
T3	66954	32779	0	0
T4	32714	0	0	0
T5	96142	32344	0	0
T6	64641	1	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	0	0	0
T14	101	0	0	0
T26	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	2	0	0
T50	0	1	0	0
T90	0	1	0	0
T135	0	31308	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	20847398	0	0
T2	64549	64453	0	0
T3	66954	31604	0	0
T4	32714	32648	0	0
T5	96142	32175	0	0
T6	64641	32417	0	0
T7	8785	0	0	0
T8	72313	33403	0	0
T9	8962	0	0	0
T10	943	0	0	0
T13	0	73765	0	0
T14	101	0	0	0
T37	0	64427	0	0
T47	0	97768	0	0
T50	0	32684	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	13689307	0	0
T1	24086	21014	0	0
T2	64549	4	0	0
T3	66954	66638	0	0
T4	32714	32652	0	0
T5	96142	4	0	0
T6	64641	4	0	0
T7	8785	8697	0	0
T8	72313	33407	0	0
T9	8962	8886	0	0
T14	101	18	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	70624	0	0
T139	115715	0	0	0
T146	73658	37975	0	0
T147	0	1	0	0
T149	0	1	0	0
T157	0	32639	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	97680	0	0	0
T165	32080	0	0	0
T166	65286	0	0	0
T167	1134	0	0	0
T168	65076	0	0	0
T169	123640	0	0	0
T170	1098	0	0	0
T171	88106	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	110	0	0
T5	96142	1	0	0
T6	64641	1	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	0	0	0
T12	82091	0	0	0
T14	101	0	0	0
T26	0	1	0	0
T38	0	11	0	0
T49	9372	0	0	0
T50	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	22063889	0	0
T2	64549	64453	0	0
T3	66954	0	0	0
T4	32714	0	0	0
T5	96142	96065	0	0
T6	64641	64575	0	0
T7	8785	0	0	0
T8	72313	38839	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	0	32379	0	0
T12	0	31679	0	0
T14	101	0	0	0
T37	0	32608	0	0
T47	0	65143	0	0
T48	0	53812	0	0
T50	0	32683	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	14608919	0	0
T1	24086	21014	0	0
T2	64549	4	0	0
T3	66954	33859	0	0
T4	32714	32652	0	0
T5	96142	32347	0	0
T6	64641	32161	0	0
T7	8785	8697	0	0
T8	72313	4	0	0
T9	8962	8886	0	0
T14	101	18	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	33408	0	0
T5	96142	1	0	0
T6	64641	1	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	0	0	0
T12	82091	0	0	0
T14	101	0	0	0
T49	9372	0	0	0
T81	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T159	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	33393	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	74964	0	0
T5	96142	3	0	0
T6	64641	1	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	0	0	0
T12	82091	0	0	0
T14	101	0	0	0
T26	0	2	0	0
T35	0	1	0	0
T36	0	7	0	0
T38	0	12	0	0
T49	9372	0	0	0
T50	0	2	0	0
T90	0	1	0	0
T138	0	2	0	0
T172	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	21106639	0	0
T2	64549	64453	0	0
T3	66954	32779	0	0
T4	32714	0	0	0
T5	96142	63719	0	0
T6	64641	32417	0	0
T7	8785	0	0	0
T8	72313	72242	0	0
T9	8962	0	0	0
T10	943	0	0	0
T13	0	73765	0	0
T14	101	0	0	0
T37	0	64427	0	0
T47	0	32625	0	0
T48	0	53812	0	0
T50	0	32683	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	14584353	0	0
T1	24086	21014	0	0
T2	64549	4	0	0
T3	66954	66638	0	0
T4	32714	32652	0	0
T5	96142	64523	0	0
T6	64641	4	0	0
T7	8785	8697	0	0
T8	72313	33407	0	0
T9	8962	8886	0	0
T14	101	18	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	99078	0	0
T16	11481	0	0	0
T40	50402	0	0	0
T141	0	1	0	0
T151	0	1	0	0
T153	106361	1	0	0
T154	67078	0	0	0
T161	0	1	0	0
T175	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	33559	0	0
T182	0	32996	0	0
T183	32890	0	0	0
T184	98221	0	0	0
T185	1124	0	0	0
T186	39573	0	0	0
T187	66755	0	0	0
T188	48243	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	121	0	0
T5	96142	1	0	0
T6	64641	1	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	0	0	0
T12	82091	0	0	0
T14	101	0	0	0
T26	0	1	0	0
T38	0	2	0	0
T49	9372	0	0	0
T50	0	2	0	0
T90	0	1	0	0
T138	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T189	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	21140378	0	0
T2	64549	64453	0	0
T3	66954	0	0	0
T4	32714	0	0	0
T5	96142	31546	0	0
T6	64641	64575	0	0
T7	8785	0	0	0
T8	72313	38839	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	0	37135	0	0
T12	0	31679	0	0
T14	101	0	0	0
T37	0	64427	0	0
T47	0	97768	0	0
T50	0	32683	0	0
T110	0	33869	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	15164162	0	0
T1	24086	21014	0	0
T2	64549	4	0	0
T3	66954	2255	0	0
T4	32714	32652	0	0
T5	96142	96070	0	0
T6	64641	4	0	0
T7	8785	8697	0	0
T8	72313	72246	0	0
T9	8962	8886	0	0
T14	101	18	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	235411	0	0
T46	0	1012	0	0
T138	68505	1	0	0
T141	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	32893	0	0
T173	39819	0	0	0
T190	0	32513	0	0
T191	0	33876	0	0
T192	0	1	0	0
T193	0	32963	0	0
T194	66779	0	0	0
T195	122345	0	0	0
T196	90	0	0	0
T197	1012	0	0	0
T198	65274	0	0	0
T199	40964	0	0	0
T200	32481	0	0	0
T201	39331	0	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	164979	0	0
T6	64641	1	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T10	943	0	0	0
T11	69602	0	0	0
T12	82091	0	0	0
T13	106216	0	0	0
T14	101	0	0	0
T26	0	1	0	0
T35	0	1	0	0
T36	0	8	0	0
T38	0	13	0	0
T49	9372	0	0	0
T50	0	1	0	0
T90	0	1	0	0
T138	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36142292	20259378	0	0
T2	64549	64453	0	0
T3	66954	64383	0	0
T4	32714	0	0	0
T5	96142	0	0	0
T6	64641	64575	0	0
T7	8785	0	0	0
T8	72313	0	0	0
T9	8962	0	0	0
T10	943	0	0	0
T12	0	31679	0	0
T13	0	38039	0	0
T14	101	0	0	0
T35	0	1372	0	0
T42	0	64326	0	0
T48	0	42437	0	0
T50	0	32683	0	0
T110	0	33869	0	0