Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1815	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1726	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1706	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1700	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1726	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1853	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1679	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1744	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1696	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1816	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1634	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1715	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1887	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1915	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1768	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1734	0	0
adc_en_ctl_rd_A	2147483647	1535	0	0
adc_fsm_rst_rd_A	2147483647	1310	0	0
adc_intr_ctl_rd_A	2147483647	1690	0	0
adc_lp_sample_ctl_rd_A	2147483647	1293	0	0
adc_pd_ctl_rd_A	2147483647	1540	0	0
adc_sample_ctl_rd_A	2147483647	1253	0	0
adc_wakeup_ctl_rd_A	2147483647	1435	0	0
intr_enable_rd_A	2147483647	2101	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1815	0	0
T15	394502	13	0	0
T16	0	20	0	0
T17	0	39	0	0
T18	0	40	0	0
T19	0	11	0	0
T20	0	22	0	0
T21	0	23	0	0
T22	0	15	0	0
T23	0	41	0	0
T24	0	17	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1726	0	0
T15	394502	21	0	0
T16	0	24	0	0
T17	0	15	0	0
T18	0	45	0	0
T19	0	29	0	0
T20	0	17	0	0
T21	0	31	0	0
T22	0	23	0	0
T23	0	45	0	0
T24	0	15	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1706	0	0
T15	394502	10	0	0
T16	0	13	0	0
T17	0	23	0	0
T18	0	38	0	0
T19	0	22	0	0
T20	0	20	0	0
T21	0	37	0	0
T22	0	13	0	0
T23	0	28	0	0
T24	0	19	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1700	0	0
T15	394502	15	0	0
T16	0	32	0	0
T17	0	22	0	0
T18	0	36	0	0
T19	0	20	0	0
T20	0	19	0	0
T21	0	31	0	0
T22	0	23	0	0
T23	0	27	0	0
T24	0	14	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1726	0	0
T15	394502	9	0	0
T16	0	31	0	0
T17	0	29	0	0
T18	0	42	0	0
T19	0	24	0	0
T20	0	16	0	0
T21	0	34	0	0
T22	0	11	0	0
T23	0	13	0	0
T24	0	17	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1853	0	0
T15	394502	28	0	0
T16	0	32	0	0
T17	0	14	0	0
T18	0	30	0	0
T19	0	12	0	0
T20	0	19	0	0
T21	0	34	0	0
T22	0	24	0	0
T23	0	43	0	0
T24	0	10	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1679	0	0
T15	394502	10	0	0
T16	0	18	0	0
T17	0	31	0	0
T18	0	41	0	0
T19	0	30	0	0
T20	0	21	0	0
T21	0	12	0	0
T22	0	18	0	0
T23	0	47	0	0
T24	0	21	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1744	0	0
T15	394502	20	0	0
T16	0	9	0	0
T17	0	30	0	0
T18	0	44	0	0
T19	0	19	0	0
T20	0	23	0	0
T21	0	44	0	0
T22	0	16	0	0
T23	0	42	0	0
T24	0	19	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1696	0	0
T15	394502	19	0	0
T16	0	26	0	0
T17	0	20	0	0
T18	0	23	0	0
T19	0	37	0	0
T20	0	17	0	0
T21	0	44	0	0
T22	0	12	0	0
T23	0	45	0	0
T24	0	23	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1816	0	0
T15	394502	9	0	0
T16	0	31	0	0
T17	0	34	0	0
T18	0	49	0	0
T19	0	4	0	0
T20	0	24	0	0
T21	0	28	0	0
T22	0	17	0	0
T23	0	40	0	0
T24	0	15	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1634	0	0
T15	394502	23	0	0
T16	0	32	0	0
T17	0	29	0	0
T18	0	38	0	0
T19	0	15	0	0
T20	0	15	0	0
T21	0	29	0	0
T22	0	20	0	0
T23	0	44	0	0
T24	0	17	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1715	0	0
T15	394502	9	0	0
T16	0	23	0	0
T17	0	17	0	0
T18	0	39	0	0
T19	0	32	0	0
T20	0	26	0	0
T21	0	15	0	0
T22	0	7	0	0
T23	0	40	0	0
T24	0	6	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1887	0	0
T15	394502	19	0	0
T16	0	20	0	0
T17	0	13	0	0
T18	0	46	0	0
T19	0	16	0	0
T20	0	19	0	0
T21	0	33	0	0
T22	0	19	0	0
T23	0	48	0	0
T24	0	19	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1915	0	0
T15	394502	26	0	0
T16	0	15	0	0
T17	0	37	0	0
T18	0	33	0	0
T19	0	15	0	0
T20	0	15	0	0
T21	0	30	0	0
T22	0	20	0	0
T23	0	40	0	0
T24	0	30	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1768	0	0
T15	394502	14	0	0
T16	0	20	0	0
T17	0	23	0	0
T18	0	32	0	0
T19	0	4	0	0
T20	0	16	0	0
T21	0	38	0	0
T22	0	15	0	0
T23	0	27	0	0
T24	0	27	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1734	0	0
T15	394502	16	0	0
T16	0	23	0	0
T17	0	24	0	0
T18	0	38	0	0
T19	0	14	0	0
T20	0	22	0	0
T21	0	32	0	0
T22	0	11	0	0
T23	0	46	0	0
T24	0	23	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1535	0	0
T15	394502	20	0	0
T16	0	21	0	0
T17	0	30	0	0
T18	0	49	0	0
T19	0	23	0	0
T20	0	23	0	0
T21	0	33	0	0
T22	0	14	0	0
T23	0	44	0	0
T24	0	19	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1310	0	0
T15	394502	17	0	0
T16	0	21	0	0
T17	0	20	0	0
T18	0	40	0	0
T19	0	25	0	0
T20	0	24	0	0
T21	0	33	0	0
T22	0	26	0	0
T23	0	37	0	0
T24	0	23	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1690	0	0
T15	394502	9	0	0
T16	0	14	0	0
T17	0	29	0	0
T18	0	22	0	0
T19	0	19	0	0
T20	0	25	0	0
T21	0	28	0	0
T22	0	19	0	0
T23	0	36	0	0
T24	0	25	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1293	0	0
T15	394502	18	0	0
T16	0	28	0	0
T17	0	15	0	0
T18	0	31	0	0
T19	0	23	0	0
T20	0	23	0	0
T21	0	33	0	0
T22	0	22	0	0
T23	0	45	0	0
T24	0	19	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1540	0	0
T15	394502	19	0	0
T16	0	15	0	0
T17	0	25	0	0
T18	0	39	0	0
T19	0	12	0	0
T20	0	19	0	0
T21	0	45	0	0
T22	0	14	0	0
T23	0	40	0	0
T24	0	23	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1253	0	0
T15	394502	7	0	0
T16	0	10	0	0
T17	0	21	0	0
T18	0	39	0	0
T19	0	17	0	0
T20	0	12	0	0
T21	0	32	0	0
T22	0	18	0	0
T23	0	40	0	0
T24	0	28	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1435	0	0
T15	394502	20	0	0
T16	0	18	0	0
T17	0	35	0	0
T18	0	41	0	0
T19	0	43	0	0
T20	0	26	0	0
T21	0	50	0	0
T22	0	14	0	0
T23	0	42	0	0
T24	0	5	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2101	0	0
T15	394502	29	0	0
T16	0	36	0	0
T17	0	31	0	0
T18	0	38	0	0
T19	0	18	0	0
T20	0	24	0	0
T21	0	96	0	0
T22	0	53	0	0
T23	0	86	0	0
T25	152129	0	0	0
T26	322029	0	0	0
T27	129412	0	0	0
T28	124071	0	0	0
T29	370772	0	0	0
T30	254568	0	0	0
T31	157320	0	0	0
T32	264303	0	0	0
T33	336061	0	0	0
T34	0	3	0	0