Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1229050	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1201591

1

T1

24

T2

451

T3

365

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2119121	1			T2	824		T4	1721		T5	2516
values[0x0]	155132	1			T1	21		T2	50		T3	465
values[0x1]	156388	1			T1	25		T2	47		T3	486

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	985564	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1445077

1

T1

26

T2

545

T3

456

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7082	1			T2	6		T5	25		T7	38
valid_sources[0x01]	7031	1			T2	2		T4	2		T5	9
valid_sources[0x02]	8283	1			T2	4		T4	15		T5	1
valid_sources[0x03]	11659	1			T5	13		T7	18		T8	11
valid_sources[0x04]	7438	1			T1	2		T2	1		T5	19
valid_sources[0x05]	13907	1			T5	34		T7	12		T8	10
valid_sources[0x06]	9249	1			T2	5		T4	19		T5	26
valid_sources[0x07]	7173	1			T2	8		T5	18		T7	27
valid_sources[0x08]	9309	1			T2	5		T4	14		T5	2
valid_sources[0x09]	8184	1			T2	2		T5	3		T7	25
valid_sources[0x0a]	24724	1			T2	14		T4	17		T5	9
valid_sources[0x0b]	9636	1			T2	4		T4	11		T5	4
valid_sources[0x0c]	6898	1			T1	1		T2	1		T5	5
valid_sources[0x0d]	8092	1			T2	7		T4	15		T5	15
valid_sources[0x0e]	7019	1			T5	7		T7	13		T8	13
valid_sources[0x0f]	21162	1			T1	1		T2	1		T5	13
valid_sources[0x10]	11106	1			T4	46		T5	10		T7	18
valid_sources[0x11]	15556	1			T2	1		T5	19		T7	28
valid_sources[0x12]	7213	1			T2	2		T4	6		T5	9
valid_sources[0x13]	7424	1			T1	1		T2	14		T5	14
valid_sources[0x14]	7680	1			T2	3		T5	22		T7	5
valid_sources[0x15]	11385	1			T2	3		T4	5		T5	12
valid_sources[0x16]	6999	1			T2	6		T4	18		T5	7
valid_sources[0x17]	7257	1			T1	1		T2	2		T5	13
valid_sources[0x18]	14018	1			T2	3		T4	3		T5	5
valid_sources[0x19]	8544	1			T5	6		T7	21		T8	11
valid_sources[0x1a]	14346	1			T2	4		T5	1		T7	18
valid_sources[0x1b]	14556	1			T2	2		T4	32		T5	8
valid_sources[0x1c]	7786	1			T2	1		T4	26		T5	8
valid_sources[0x1d]	7650	1			T5	14		T7	31		T8	19
valid_sources[0x1e]	8155	1			T2	5		T5	8		T7	30
valid_sources[0x1f]	11564	1			T2	2		T4	2		T5	9
valid_sources[0x20]	7975	1			T2	11		T5	8		T7	16
valid_sources[0x21]	17580	1			T2	9		T4	30		T5	4
valid_sources[0x22]	11605	1			T2	16		T5	8		T7	27
valid_sources[0x23]	9480	1			T5	13		T7	9		T8	4
valid_sources[0x24]	9630	1			T4	4		T5	17		T7	15
valid_sources[0x25]	7101	1			T1	1		T5	12		T7	6
valid_sources[0x26]	6817	1			T1	1		T2	3		T4	1
valid_sources[0x27]	7166	1			T2	8		T7	11		T8	12
valid_sources[0x28]	9172	1			T4	1		T5	17		T7	15
valid_sources[0x29]	11371	1			T2	1		T5	24		T7	6
valid_sources[0x2a]	6919	1			T1	1		T4	3		T5	23
valid_sources[0x2b]	7020	1			T5	20		T7	19		T10	3
valid_sources[0x2c]	8461	1			T5	13		T7	20		T8	8
valid_sources[0x2d]	7490	1			T2	8		T4	17		T5	8
valid_sources[0x2e]	7615	1			T1	2		T2	16		T4	1
valid_sources[0x2f]	10427	1			T5	6		T7	25		T8	17
valid_sources[0x30]	8119	1			T1	1		T4	31		T5	9
valid_sources[0x31]	9062	1			T2	3		T5	7		T7	17
valid_sources[0x32]	6917	1			T5	16		T7	25		T8	20
valid_sources[0x33]	8303	1			T2	4		T4	5		T5	9
valid_sources[0x34]	6967	1			T2	2		T5	6		T7	19
valid_sources[0x35]	11436	1			T4	20		T5	1		T7	20
valid_sources[0x36]	7144	1			T4	4		T5	26		T7	11
valid_sources[0x37]	11590	1			T2	4		T4	3		T5	14
valid_sources[0x38]	8103	1			T5	18		T7	17		T8	6
valid_sources[0x39]	7105	1			T5	15		T7	15		T8	1
valid_sources[0x3a]	7172	1			T2	12		T5	6		T7	12
valid_sources[0x3b]	7187	1			T2	5		T5	15		T7	17
valid_sources[0x3c]	11816	1			T2	3		T4	29		T5	6
valid_sources[0x3d]	7338	1			T1	2		T2	14		T4	41
valid_sources[0x3e]	15773	1			T4	16		T5	19		T7	18
valid_sources[0x3f]	8099	1			T1	1		T2	6		T3	951
valid_sources[0x40]	6953	1			T2	11		T4	7		T5	2
valid_sources[0x41]	23484	1			T2	9		T5	8		T7	16
valid_sources[0x42]	6925	1			T4	17		T5	20		T7	10
valid_sources[0x43]	8356	1			T4	3		T5	4		T7	28
valid_sources[0x44]	11413	1			T2	16		T5	5		T7	8
valid_sources[0x45]	9227	1			T2	1		T4	3		T5	6
valid_sources[0x46]	8293	1			T2	11		T4	18		T5	17
valid_sources[0x47]	16183	1			T2	3		T4	7		T5	16
valid_sources[0x48]	6936	1			T5	4		T7	19		T8	3
valid_sources[0x49]	12658	1			T4	39		T5	19		T7	14
valid_sources[0x4a]	7905	1			T2	12		T5	2		T7	26
valid_sources[0x4b]	8489	1			T5	11		T7	12		T8	32
valid_sources[0x4c]	7910	1			T2	2		T4	1		T5	4
valid_sources[0x4d]	16141	1			T2	4		T4	5		T5	5
valid_sources[0x4e]	8503	1			T2	5		T4	12		T5	6
valid_sources[0x4f]	7095	1			T4	67		T5	7		T7	18
valid_sources[0x50]	7137	1			T4	19		T5	6		T7	15
valid_sources[0x51]	7572	1			T2	5		T4	3		T5	1
valid_sources[0x52]	7891	1			T2	2		T4	2		T5	5
valid_sources[0x53]	7348	1			T2	1		T4	38		T5	4
valid_sources[0x54]	7711	1			T4	20		T5	10		T7	28
valid_sources[0x55]	8107	1			T2	16		T5	14		T7	16
valid_sources[0x56]	10930	1			T2	2		T5	9		T7	8
valid_sources[0x57]	11230	1			T2	3		T4	1		T5	4
valid_sources[0x58]	8622	1			T5	7		T7	20		T8	1
valid_sources[0x59]	7912	1			T2	4		T5	4		T7	12
valid_sources[0x5a]	7953	1			T4	17		T5	7		T7	7
valid_sources[0x5b]	7306	1			T1	1		T2	4		T4	18
valid_sources[0x5c]	7357	1			T1	1		T2	16		T5	7
valid_sources[0x5d]	7321	1			T2	7		T4	3		T5	30
valid_sources[0x5e]	7544	1			T2	4		T5	13		T7	12
valid_sources[0x5f]	7032	1			T1	1		T4	4		T5	9
valid_sources[0x60]	11942	1			T2	9		T4	5		T5	7
valid_sources[0x61]	9917	1			T2	8		T4	16		T5	7
valid_sources[0x62]	8311	1			T2	5		T4	1		T5	13
valid_sources[0x63]	8951	1			T2	5		T5	13		T7	30
valid_sources[0x64]	6953	1			T5	25		T7	9		T9	1
valid_sources[0x65]	6920	1			T4	17		T5	6		T7	18
valid_sources[0x66]	7329	1			T2	7		T4	18		T5	3
valid_sources[0x67]	18656	1			T2	2		T4	12		T5	12
valid_sources[0x68]	13384	1			T2	3		T5	10		T7	25
valid_sources[0x69]	8333	1			T1	1		T5	9		T7	17
valid_sources[0x6a]	7777	1			T1	1		T2	3		T5	23
valid_sources[0x6b]	10047	1			T4	16		T5	5		T7	20
valid_sources[0x6c]	8749	1			T2	3		T4	14		T5	13
valid_sources[0x6d]	11943	1			T4	5		T5	5		T7	9
valid_sources[0x6e]	10010	1			T2	9		T4	7		T5	12
valid_sources[0x6f]	7399	1			T4	10		T5	3		T7	9
valid_sources[0x70]	10389	1			T1	1		T2	10		T4	2
valid_sources[0x71]	11515	1			T4	2		T5	19		T7	16
valid_sources[0x72]	7443	1			T5	2		T7	16		T8	6
valid_sources[0x73]	7509	1			T5	6		T7	22		T8	5
valid_sources[0x74]	11343	1			T2	6		T4	7		T5	12
valid_sources[0x75]	11570	1			T2	4		T4	9		T5	10
valid_sources[0x76]	6960	1			T5	11		T7	26		T8	16
valid_sources[0x77]	9708	1			T2	2		T5	7		T7	16
valid_sources[0x78]	7101	1			T2	3		T4	14		T5	5
valid_sources[0x79]	7616	1			T1	1		T5	4		T7	10
valid_sources[0x7a]	17260	1			T2	7		T4	4		T5	17
valid_sources[0x7b]	13284	1			T2	4		T5	3		T7	25
valid_sources[0x7c]	7461	1			T2	1		T4	11		T5	10
valid_sources[0x7d]	7206	1			T2	3		T4	2		T5	20
valid_sources[0x7e]	9955	1			T4	5		T5	5		T7	26
valid_sources[0x7f]	14066	1			T4	7		T5	18		T7	24
valid_sources[0x80]	7391	1			T4	22		T5	8		T7	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1055332

1

T2

409

T4

864

T5

1246

values[0x0]

all_enables

biggest_size

84606

1

T1

12

T2

23

T3

212

values[0x1]

all_enables

biggest_size

61653

1

T1

12

T2

19

T3

153