Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31373	1			T2	11		T3	279		T4	19
auto[PWRUP]	132	1			T58	2		T56	1		T178	3
auto[ONEST_0]	94	1			T58	2		T56	2		T178	2
auto[ONEST_021]	15	1			T3	1		T57	1		T191	1
auto[ONEST_1]	94	1			T3	1		T57	2		T58	2
auto[ONEST_DONE]	5	1			T11	1		T192	1		T193	1
auto[LP_0]	164	1			T3	1		T11	1		T58	1
auto[LP_021]	33	1			T11	1		T27	1		T194	1
auto[LP_1]	140	1			T3	3		T11	3		T57	1
auto[LP_EVAL]	100	1			T3	1		T36	2		T56	1
auto[LP_SLP]	541	1			T3	10		T11	6		T57	8
auto[LP_PWRUP]	29	1			T57	1		T14	1		T134	1
auto[NP_0]	169	1			T3	3		T11	2		T57	1
auto[NP_021]	29	1			T57	1		T56	1		T178	1
auto[NP_1]	169	1			T3	1		T11	2		T58	2
auto[NP_EVAL]	32	1			T11	1		T57	1		T194	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T14

1

T17

1

T33

1

min

30789

1

T2

11

T3

273

T4

19

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30800	1			T2	11		T3	273		T4	19
pow[0x1]	11	1			T11	1		T58	1		T178	1
pow[0x2]	17	1			T57	1		T178	1		T195	1
pow[0x3]	34	1			T3	2		T57	1		T194	3
pow[0x4]	60	1			T3	1		T57	1		T58	2
pow[0x5]	140	1			T3	2		T57	2		T36	1
pow[0x6]	286	1			T3	3		T11	6		T57	2
pow[0x7]	584	1			T3	6		T11	6		T57	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

190

1

T3

1

T11

1

T57

1

min

30263

1

T2

11

T3

264

T4

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30263	1			T2	11		T3	264		T4	19
pow[0x5]	3	1			T33	1		T196	1		T197	1
pow[0x6]	1	1			T198	1		-	-		-	-
pow[0x7]	1	1			T199	1		-	-		-	-
pow[0x8]	6	1			T200	1		T201	1		T33	1
pow[0x9]	9	1			T3	1		T195	1		T17	1
pow[0xa]	21	1			T194	1		T202	1		T163	1
pow[0xb]	37	1			T3	1		T14	1		T27	1
pow[0xc]	89	1			T3	1		T11	2		T57	1
pow[0xd]	162	1			T3	3		T11	2		T57	3
pow[0xe]	345	1			T3	8		T11	3		T58	6
pow[0xf]	664	1			T3	7		T11	2		T57	4