Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2512	1			T3	16		T11	16		T55	3
auto[PWRUP]	168	1			T3	1		T11	1		T57	2
auto[ONEST_0]	96	1			T3	1		T58	1		T195	3
auto[ONEST_021]	21	1			T27	1		T325	1		T191	1
auto[ONEST_1]	95	1			T3	2		T11	3		T57	1
auto[ONEST_DONE]	5	1			T57	1		T134	1		T326	1
auto[LP_0]	134	1			T3	2		T11	1		T57	2
auto[LP_021]	38	1			T11	1		T56	2		T327	2
auto[LP_1]	179	1			T3	3		T11	2		T58	1
auto[LP_EVAL]	69	1			T3	2		T11	1		T36	1
auto[LP_SLP]	618	1			T3	5		T11	3		T57	8
auto[LP_PWRUP]	31	1			T58	1		T14	2		T200	1
auto[NP_0]	238	1			T3	2		T57	1		T37	1
auto[NP_021]	41	1			T3	1		T39	1		T15	2
auto[NP_1]	235	1			T3	1		T11	1		T57	1
auto[NP_EVAL]	37	1			T57	1		T36	2		T37	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T11

1

T202

1

T328

1

min

2144

1

T3

6

T11

10

T55

3

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2160	1			T3	6		T11	10		T55	3
pow[0x1]	13	1			T3	1		T195	1		T27	1
pow[0x2]	26	1			T3	1		T11	1		T58	1
pow[0x3]	43	1			T56	1		T195	2		T14	5
pow[0x4]	97	1			T3	2		T57	1		T56	3
pow[0x5]	130	1			T3	2		T11	2		T57	1
pow[0x6]	296	1			T3	2		T11	3		T57	3
pow[0x7]	583	1			T3	4		T11	7		T57	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

219

1

T3

2

T11

3

T57

1

min

1424

1

T3

1

T11

6

T55

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1426	1			T3	1		T11	6		T55	3
pow[0x1]	22	1			T39	4		T50	1		T51	1
pow[0x2]	15	1			T15	4		T17	1		T217	1
pow[0x3]	52	1			T38	1		T14	5		T15	1
pow[0x4]	64	1			T36	4		T37	3		T38	4
pow[0x5]	1	1			T16	1		-	-		-	-
pow[0x7]	5	1			T328	1		T329	2		T330	1
pow[0x8]	4	1			T202	1		T331	1		T157	1
pow[0x9]	14	1			T57	2		T200	1		T191	1
pow[0xa]	17	1			T14	1		T27	2		T163	1
pow[0xb]	57	1			T3	1		T58	2		T178	1
pow[0xc]	97	1			T3	2		T11	2		T57	4
pow[0xd]	156	1			T3	2		T11	1		T57	2
pow[0xe]	320	1			T3	4		T11	3		T57	3
pow[0xf]	662	1			T3	6		T11	6		T57	6