Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1247049	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1219277

1

T1

2682

T2

59

T3

454

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2159226	1			T1	4996		T2	81		T4	81
values[0x0]	153229	1			T1	199		T2	32		T3	534
values[0x1]	153871	1			T1	205		T2	31		T3	551

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	998811	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1467515

1

T1

3217

T2

67

T3

525

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9201	1			T1	12		T2	3		T3	7
valid_sources[0x01]	12052	1			T1	28		T3	4		T4	3
valid_sources[0x02]	10785	1			T1	12		T3	1		T4	2
valid_sources[0x03]	7338	1			T1	16		T3	29		T5	7
valid_sources[0x04]	8252	1			T1	18		T3	1		T5	3
valid_sources[0x05]	7757	1			T1	21		T3	2		T5	2
valid_sources[0x06]	7760	1			T1	12		T3	13		T5	1
valid_sources[0x07]	7288	1			T1	24		T3	14		T5	4
valid_sources[0x08]	8275	1			T1	16		T4	2		T5	4
valid_sources[0x09]	8704	1			T1	25		T5	2		T6	19
valid_sources[0x0a]	7738	1			T1	22		T2	1		T3	12
valid_sources[0x0b]	7238	1			T1	17		T3	8		T5	2
valid_sources[0x0c]	7754	1			T1	33		T5	2		T6	29
valid_sources[0x0d]	7352	1			T1	25		T3	17		T4	1
valid_sources[0x0e]	9204	1			T1	22		T3	3		T4	2
valid_sources[0x0f]	11631	1			T1	19		T3	3		T5	8
valid_sources[0x10]	12749	1			T1	15		T3	1		T4	5
valid_sources[0x11]	7400	1			T1	14		T2	1		T3	12
valid_sources[0x12]	11913	1			T1	17		T3	9		T4	1
valid_sources[0x13]	10496	1			T1	11		T2	1		T3	5
valid_sources[0x14]	14445	1			T1	41		T3	7		T4	3
valid_sources[0x15]	20107	1			T1	21		T3	8		T5	4
valid_sources[0x16]	12016	1			T1	20		T3	9		T5	4
valid_sources[0x17]	12813	1			T1	15		T3	7		T5	4
valid_sources[0x18]	8809	1			T1	22		T2	3		T3	3
valid_sources[0x19]	19946	1			T1	23		T5	4		T6	10
valid_sources[0x1a]	7370	1			T1	29		T3	8		T5	5
valid_sources[0x1b]	11777	1			T1	18		T3	3		T4	1
valid_sources[0x1c]	10493	1			T1	18		T3	5		T5	1
valid_sources[0x1d]	7277	1			T1	22		T2	1		T3	3
valid_sources[0x1e]	11346	1			T1	22		T3	7		T5	2
valid_sources[0x1f]	7374	1			T1	19		T3	1		T5	1
valid_sources[0x20]	8226	1			T1	31		T3	8		T5	7
valid_sources[0x21]	11148	1			T1	19		T3	2		T4	1
valid_sources[0x22]	8412	1			T1	33		T2	3		T3	1
valid_sources[0x23]	7813	1			T1	20		T3	6		T5	5
valid_sources[0x24]	8409	1			T1	20		T3	5		T5	3
valid_sources[0x25]	9476	1			T1	18		T5	8		T6	20
valid_sources[0x26]	11846	1			T1	24		T3	2		T4	1
valid_sources[0x27]	8240	1			T1	26		T2	4		T3	9
valid_sources[0x28]	7613	1			T1	28		T3	1		T4	1
valid_sources[0x29]	12462	1			T1	18		T3	7		T5	3
valid_sources[0x2a]	11813	1			T1	15		T2	3		T3	1
valid_sources[0x2b]	7823	1			T1	22		T3	1		T5	8
valid_sources[0x2c]	8966	1			T1	22		T3	3		T4	1
valid_sources[0x2d]	8650	1			T1	9		T5	8		T6	9
valid_sources[0x2e]	7604	1			T1	25		T3	1		T4	2
valid_sources[0x2f]	7353	1			T1	18		T3	1		T4	1
valid_sources[0x30]	11839	1			T1	20		T3	3		T5	1
valid_sources[0x31]	7577	1			T1	21		T3	4		T6	7
valid_sources[0x32]	7360	1			T1	19		T2	3		T3	2
valid_sources[0x33]	12459	1			T1	11		T2	3		T3	1
valid_sources[0x34]	10380	1			T1	22		T3	2		T5	7
valid_sources[0x35]	7499	1			T1	14		T3	10		T5	2
valid_sources[0x36]	7290	1			T1	17		T2	1		T5	3
valid_sources[0x37]	7479	1			T1	23		T3	7		T5	4
valid_sources[0x38]	7291	1			T1	24		T3	8		T4	3
valid_sources[0x39]	7781	1			T1	16		T3	8		T4	1
valid_sources[0x3a]	10318	1			T1	15		T2	1		T3	3
valid_sources[0x3b]	9927	1			T1	20		T2	1		T3	7
valid_sources[0x3c]	10351	1			T1	26		T2	2		T3	5
valid_sources[0x3d]	11736	1			T1	15		T3	1		T5	4
valid_sources[0x3e]	7465	1			T1	24		T2	1		T3	9
valid_sources[0x3f]	15695	1			T1	22		T3	5		T4	2
valid_sources[0x40]	11706	1			T1	24		T5	3		T6	27
valid_sources[0x41]	11669	1			T1	20		T3	4		T5	5
valid_sources[0x42]	7185	1			T1	18		T2	7		T3	2
valid_sources[0x43]	12016	1			T1	20		T2	1		T3	2
valid_sources[0x44]	9448	1			T1	20		T2	2		T3	2
valid_sources[0x45]	11953	1			T1	26		T3	2		T4	3
valid_sources[0x46]	7767	1			T1	24		T3	3		T4	1
valid_sources[0x47]	7361	1			T1	26		T3	8		T5	9
valid_sources[0x48]	8105	1			T1	20		T3	1		T5	3
valid_sources[0x49]	13498	1			T1	17		T3	5		T5	4
valid_sources[0x4a]	7502	1			T1	21		T3	3		T4	1
valid_sources[0x4b]	7343	1			T1	27		T3	5		T5	3
valid_sources[0x4c]	7253	1			T1	18		T3	1		T5	2
valid_sources[0x4d]	11899	1			T1	22		T3	12		T5	4
valid_sources[0x4e]	11838	1			T1	26		T3	5		T5	7
valid_sources[0x4f]	9198	1			T1	34		T2	1		T4	1
valid_sources[0x50]	20912	1			T1	16		T3	8		T5	1
valid_sources[0x51]	7816	1			T1	23		T3	2		T5	2
valid_sources[0x52]	9179	1			T1	19		T3	10		T5	3
valid_sources[0x53]	17905	1			T1	20		T3	6		T5	7
valid_sources[0x54]	8493	1			T1	18		T3	5		T4	1
valid_sources[0x55]	7661	1			T1	14		T5	17		T6	16
valid_sources[0x56]	11680	1			T1	20		T2	1		T3	4
valid_sources[0x57]	7466	1			T1	16		T3	9		T6	10
valid_sources[0x58]	12310	1			T1	20		T3	2		T5	1
valid_sources[0x59]	8447	1			T1	23		T5	1		T6	29
valid_sources[0x5a]	9988	1			T1	23		T3	4		T5	2
valid_sources[0x5b]	7143	1			T1	14		T3	11		T6	24
valid_sources[0x5c]	7876	1			T1	23		T2	2		T3	7
valid_sources[0x5d]	7312	1			T1	27		T2	4		T3	6
valid_sources[0x5e]	8751	1			T1	27		T3	3		T5	8
valid_sources[0x5f]	11177	1			T1	27		T3	1		T4	1
valid_sources[0x60]	7656	1			T1	16		T2	4		T3	5
valid_sources[0x61]	7310	1			T1	12		T2	1		T3	1
valid_sources[0x62]	9006	1			T1	18		T4	1		T5	12
valid_sources[0x63]	8010	1			T1	33		T3	2		T4	3
valid_sources[0x64]	13095	1			T1	17		T2	1		T3	1
valid_sources[0x65]	8822	1			T1	28		T5	2		T6	26
valid_sources[0x66]	8017	1			T1	23		T2	4		T3	1
valid_sources[0x67]	14682	1			T1	20		T3	3		T4	1
valid_sources[0x68]	12956	1			T1	17		T4	1		T5	18
valid_sources[0x69]	12328	1			T1	28		T3	2		T5	2
valid_sources[0x6a]	7090	1			T1	23		T2	1		T3	10
valid_sources[0x6b]	7830	1			T1	14		T3	9		T5	16
valid_sources[0x6c]	7439	1			T1	21		T5	2		T6	18
valid_sources[0x6d]	7518	1			T1	18		T4	1		T6	18
valid_sources[0x6e]	8622	1			T1	20		T3	12		T5	6
valid_sources[0x6f]	8440	1			T1	22		T2	3		T3	7
valid_sources[0x70]	7457	1			T1	25		T3	1		T4	2
valid_sources[0x71]	12591	1			T1	19		T3	2		T5	3
valid_sources[0x72]	7591	1			T1	24		T3	5		T5	7
valid_sources[0x73]	7818	1			T1	28		T3	1		T6	18
valid_sources[0x74]	11532	1			T1	31		T3	16		T5	6
valid_sources[0x75]	7764	1			T1	13		T3	2		T4	1
valid_sources[0x76]	10491	1			T1	21		T3	11		T5	2
valid_sources[0x77]	7594	1			T1	20		T6	20		T7	24
valid_sources[0x78]	7257	1			T1	25		T2	1		T3	5
valid_sources[0x79]	12775	1			T1	31		T2	3		T3	6
valid_sources[0x7a]	7117	1			T1	28		T3	4		T5	4
valid_sources[0x7b]	7772	1			T1	26		T5	3		T6	19
valid_sources[0x7c]	13830	1			T1	19		T3	9		T5	2
valid_sources[0x7d]	7683	1			T1	22		T3	3		T5	10
valid_sources[0x7e]	8327	1			T1	24		T3	4		T4	1
valid_sources[0x7f]	10235	1			T1	32		T3	13		T5	2
valid_sources[0x80]	7462	1			T1	20		T2	2		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1075055

1

T1

2519

T2

42

T4

37

values[0x0]

all_enables

biggest_size

83849

1

T1

102

T2

10

T3

252

values[0x1]

all_enables

biggest_size

60373

1

T1

61

T2

7

T3

202