Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28399	1			T1	17		T3	236		T6	23
auto[PWRUP]	111	1			T8	3		T15	3		T37	2
auto[ONEST_0]	44	1			T38	2		T42	1		T76	2
auto[ONEST_021]	11	1			T15	1		T76	1		T39	1
auto[ONEST_1]	86	1			T3	1		T8	2		T37	3
auto[ONEST_DONE]	2	1			T40	1		T181	1		-	-
auto[LP_0]	118	1			T3	1		T8	2		T27	1
auto[LP_021]	31	1			T8	1		T37	1		T39	1
auto[LP_1]	129	1			T3	2		T8	1		T27	2
auto[LP_EVAL]	82	1			T8	1		T27	2		T37	1
auto[LP_SLP]	528	1			T3	11		T8	3		T27	3
auto[LP_PWRUP]	20	1			T3	1		T38	1		T42	1
auto[NP_0]	151	1			T3	3		T8	2		T27	1
auto[NP_021]	35	1			T15	1		T37	1		T38	1
auto[NP_1]	152	1			T3	1		T8	2		T27	1
auto[NP_EVAL]	37	1			T8	1		T37	2		T39	3

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T15

1

T182

1

T41

1

min

27885

1

T1

17

T3

235

T6

23

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27891	1			T1	17		T3	235		T6	23
pow[0x1]	8	1			T183	1		T184	1		T185	1
pow[0x2]	17	1			T15	1		T76	1		T186	1
pow[0x3]	19	1			T38	2		T187	1		T40	1
pow[0x4]	91	1			T8	3		T37	3		T38	1
pow[0x5]	133	1			T3	3		T8	5		T15	3
pow[0x6]	267	1			T3	2		T8	3		T15	2
pow[0x7]	505	1			T3	7		T8	12		T27	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

186

1

T3

3

T8

1

T15

3

min

27394

1

T1

17

T3

223

T6

23

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27394	1			T1	17		T3	223		T6	23
pow[0x4]	1	1			T40	1		-	-		-	-
pow[0x5]	2	1			T188	1		T189	1		-	-
pow[0x7]	4	1			T27	1		T182	1		T190	1
pow[0x8]	2	1			T186	1		T191	1		-	-
pow[0x9]	11	1			T37	1		T38	1		T39	1
pow[0xa]	10	1			T37	1		T190	1		T192	1
pow[0xb]	41	1			T8	1		T38	2		T42	1
pow[0xc]	74	1			T15	1		T37	2		T38	1
pow[0xd]	156	1			T3	1		T27	3		T15	3
pow[0xe]	297	1			T3	7		T8	3		T27	1
pow[0xf]	582	1			T3	10		T8	8		T27	6