Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2366	1			T1	3		T3	20		T5	18
auto[PWRUP]	147	1			T3	2		T8	1		T27	2
auto[ONEST_0]	100	1			T3	3		T8	3		T27	1
auto[ONEST_021]	23	1			T3	1		T42	1		T187	1
auto[ONEST_1]	92	1			T3	2		T27	2		T38	2
auto[ONEST_DONE]	1	1			T321	1		-	-		-	-
auto[LP_0]	120	1			T3	3		T8	1		T15	3
auto[LP_021]	28	1			T37	1		T38	1		T187	2
auto[LP_1]	148	1			T3	2		T8	2		T27	1
auto[LP_EVAL]	65	1			T3	1		T8	1		T37	1
auto[LP_SLP]	539	1			T3	6		T5	1		T8	7
auto[LP_PWRUP]	32	1			T3	1		T28	1		T38	1
auto[NP_0]	214	1			T3	4		T5	1		T8	4
auto[NP_021]	50	1			T5	1		T27	1		T15	1
auto[NP_1]	230	1			T3	1		T5	3		T8	2
auto[NP_EVAL]	24	1			T15	1		T37	1		T39	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T188

2

T322

1

T190

1

min

2024

1

T1

3

T3

9

T5

24

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2038	1			T1	3		T3	9		T5	24
pow[0x1]	7	1			T16	1		T192	1		T323	1
pow[0x2]	24	1			T3	1		T8	1		T27	1
pow[0x3]	42	1			T8	1		T37	2		T187	1
pow[0x4]	55	1			T3	2		T38	1		T187	2
pow[0x5]	134	1			T3	3		T8	2		T27	1
pow[0x6]	254	1			T3	7		T8	3		T27	1
pow[0x7]	536	1			T3	9		T8	5		T27	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

203

1

T3

2

T15

1

T16

1

min

1407

1

T1

3

T3

2

T5

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1408	1			T1	3		T3	2		T5	20
pow[0x1]	15	1			T15	4		T30	1		T88	2
pow[0x2]	29	1			T5	1		T27	5		T15	3
pow[0x3]	56	1			T14	2		T28	3		T30	1
pow[0x4]	49	1			T5	3		T28	1		T16	3
pow[0x6]	1	1			T186	1		-	-		-	-
pow[0x8]	4	1			T324	1		T325	1		T326	1
pow[0x9]	7	1			T3	1		T186	1		T325	1
pow[0xa]	18	1			T76	1		T182	1		T223	1
pow[0xb]	36	1			T3	1		T76	1		T39	1
pow[0xc]	70	1			T3	1		T8	1		T15	1
pow[0xd]	139	1			T3	5		T8	1		T37	1
pow[0xe]	315	1			T3	8		T8	10		T27	2
pow[0xf]	623	1			T3	12		T8	11		T27	4