Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	3304	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	3383	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	3221	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	3235	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	3082	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	3242	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	3299	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	3441	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	3300	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	3254	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	3248	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	3231	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	3234	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	3172	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	3057	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	3132	0	0
adc_en_ctl_rd_A	2147483647	2821	0	0
adc_fsm_rst_rd_A	2147483647	2607	0	0
adc_intr_ctl_rd_A	2147483647	3244	0	0
adc_lp_sample_ctl_rd_A	2147483647	2639	0	0
adc_pd_ctl_rd_A	2147483647	3040	0	0
adc_sample_ctl_rd_A	2147483647	2574	0	0
adc_wakeup_ctl_rd_A	2147483647	2858	0	0
intr_enable_rd_A	2147483647	3477	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3304	0	0
T5	927226	25	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	15	0	0
T15	0	14	0	0
T16	0	35	0	0
T17	0	16	0	0
T18	0	46	0	0
T19	0	21	0	0
T20	0	14	0	0
T21	0	21	0	0
T22	0	25	0	0
T23	250634	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3383	0	0
T5	927226	34	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	24	0	0
T15	0	25	0	0
T16	0	30	0	0
T17	0	33	0	0
T18	0	33	0	0
T19	0	27	0	0
T20	0	18	0	0
T21	0	17	0	0
T22	0	22	0	0
T23	250634	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3221	0	0
T5	927226	24	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	21	0	0
T15	0	19	0	0
T16	0	22	0	0
T17	0	23	0	0
T18	0	37	0	0
T19	0	23	0	0
T20	0	19	0	0
T21	0	18	0	0
T22	0	19	0	0
T23	250634	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3235	0	0
T5	927226	32	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	29	0	0
T15	0	14	0	0
T16	0	33	0	0
T17	0	29	0	0
T18	0	24	0	0
T19	0	19	0	0
T20	0	12	0	0
T21	0	16	0	0
T22	0	25	0	0
T23	250634	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3082	0	0
T5	927226	22	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	10	0	0
T15	0	29	0	0
T16	0	27	0	0
T17	0	19	0	0
T18	0	41	0	0
T19	0	24	0	0
T20	0	16	0	0
T21	0	31	0	0
T22	0	34	0	0
T23	250634	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3242	0	0
T5	927226	14	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	29	0	0
T15	0	23	0	0
T16	0	33	0	0
T17	0	23	0	0
T18	0	20	0	0
T19	0	25	0	0
T20	0	23	0	0
T21	0	12	0	0
T22	0	27	0	0
T23	250634	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3299	0	0
T5	927226	26	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	12	0	0
T15	0	34	0	0
T16	0	6	0	0
T17	0	30	0	0
T18	0	35	0	0
T19	0	17	0	0
T20	0	14	0	0
T21	0	24	0	0
T22	0	34	0	0
T23	250634	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3441	0	0
T5	927226	28	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	28	0	0
T15	0	41	0	0
T16	0	16	0	0
T17	0	19	0	0
T18	0	37	0	0
T19	0	20	0	0
T20	0	15	0	0
T21	0	24	0	0
T22	0	24	0	0
T23	250634	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3300	0	0
T5	927226	36	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	23	0	0
T15	0	27	0	0
T16	0	22	0	0
T17	0	18	0	0
T18	0	30	0	0
T19	0	10	0	0
T20	0	12	0	0
T21	0	22	0	0
T22	0	33	0	0
T23	250634	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3254	0	0
T5	927226	26	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	12	0	0
T15	0	22	0	0
T16	0	33	0	0
T17	0	10	0	0
T18	0	36	0	0
T19	0	23	0	0
T20	0	10	0	0
T21	0	9	0	0
T22	0	28	0	0
T23	250634	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3248	0	0
T5	927226	28	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	19	0	0
T15	0	24	0	0
T16	0	35	0	0
T17	0	22	0	0
T18	0	24	0	0
T19	0	18	0	0
T20	0	28	0	0
T21	0	25	0	0
T22	0	27	0	0
T23	250634	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3231	0	0
T5	927226	25	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	24	0	0
T15	0	30	0	0
T16	0	44	0	0
T17	0	22	0	0
T18	0	31	0	0
T19	0	18	0	0
T20	0	16	0	0
T21	0	17	0	0
T22	0	26	0	0
T23	250634	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3234	0	0
T5	927226	17	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	18	0	0
T15	0	23	0	0
T16	0	42	0	0
T17	0	26	0	0
T18	0	36	0	0
T19	0	27	0	0
T20	0	19	0	0
T21	0	15	0	0
T22	0	53	0	0
T23	250634	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3172	0	0
T5	927226	25	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	15	0	0
T15	0	21	0	0
T16	0	24	0	0
T17	0	20	0	0
T18	0	32	0	0
T19	0	22	0	0
T20	0	34	0	0
T21	0	24	0	0
T22	0	26	0	0
T23	250634	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3057	0	0
T5	927226	29	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	19	0	0
T15	0	35	0	0
T16	0	31	0	0
T17	0	28	0	0
T18	0	25	0	0
T19	0	13	0	0
T20	0	23	0	0
T21	0	28	0	0
T22	0	28	0	0
T23	250634	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3132	0	0
T5	927226	40	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	19	0	0
T15	0	7	0	0
T16	0	21	0	0
T17	0	29	0	0
T18	0	22	0	0
T19	0	22	0	0
T20	0	13	0	0
T21	0	23	0	0
T22	0	30	0	0
T23	250634	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2821	0	0
T5	927226	26	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	15	0	0
T15	0	13	0	0
T16	0	19	0	0
T17	0	25	0	0
T18	0	36	0	0
T19	0	6	0	0
T20	0	28	0	0
T21	0	14	0	0
T22	0	34	0	0
T23	250634	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2607	0	0
T5	927226	36	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	33	0	0
T15	0	21	0	0
T16	0	22	0	0
T17	0	12	0	0
T18	0	29	0	0
T19	0	17	0	0
T20	0	19	0	0
T21	0	17	0	0
T22	0	40	0	0
T23	250634	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3244	0	0
T5	927226	31	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	15	0	0
T15	0	43	0	0
T16	0	23	0	0
T17	0	17	0	0
T18	0	36	0	0
T19	0	11	0	0
T20	0	18	0	0
T21	0	17	0	0
T22	0	35	0	0
T23	250634	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2639	0	0
T5	927226	37	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	15	0	0
T15	0	39	0	0
T16	0	36	0	0
T17	0	26	0	0
T18	0	52	0	0
T19	0	18	0	0
T20	0	15	0	0
T21	0	29	0	0
T22	0	38	0	0
T23	250634	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3040	0	0
T5	927226	19	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	25	0	0
T15	0	19	0	0
T16	0	33	0	0
T17	0	34	0	0
T18	0	37	0	0
T19	0	18	0	0
T20	0	10	0	0
T21	0	23	0	0
T22	0	26	0	0
T23	250634	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2574	0	0
T5	927226	30	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	17	0	0
T15	0	29	0	0
T16	0	46	0	0
T17	0	17	0	0
T18	0	27	0	0
T19	0	18	0	0
T20	0	27	0	0
T21	0	26	0	0
T22	0	39	0	0
T23	250634	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2858	0	0
T5	927226	34	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T11	490524	0	0	0
T12	986157	0	0	0
T13	112122	0	0	0
T14	0	25	0	0
T15	0	22	0	0
T16	0	17	0	0
T17	0	29	0	0
T18	0	20	0	0
T19	0	21	0	0
T20	0	11	0	0
T21	0	15	0	0
T22	0	20	0	0
T23	250634	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3477	0	0
T1	330544	19	0	0
T2	572978	0	0	0
T3	111319	0	0	0
T4	137790	0	0	0
T5	927226	101	0	0
T6	104098	0	0	0
T7	743710	0	0	0
T8	875530	0	0	0
T9	775934	0	0	0
T10	159645	0	0	0
T14	0	56	0	0
T15	0	43	0	0
T16	0	45	0	0
T17	0	21	0	0
T18	0	50	0	0
T24	0	4	0	0
T25	0	8	0	0
T26	0	3	0	0