Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1226384	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1206150

1

T1

285

T2

2657

T3

2124

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2124149	1			T2	4801		T3	4036		T4	81
values[0x0]	153470	1			T1	376		T2	263		T3	111
values[0x1]	154915	1			T1	405		T2	304		T3	106

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	981993	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1450541

1

T1

350

T2

3165

T3

2533

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8480	1			T1	3		T2	22		T3	14
valid_sources[0x01]	6913	1			T1	4		T2	22		T3	19
valid_sources[0x02]	7348	1			T1	3		T2	28		T3	12
valid_sources[0x03]	7152	1			T1	1		T2	21		T3	22
valid_sources[0x04]	8572	1			T1	5		T2	24		T3	25
valid_sources[0x05]	8768	1			T1	4		T2	21		T3	16
valid_sources[0x06]	8612	1			T1	4		T2	16		T3	22
valid_sources[0x07]	11915	1			T1	5		T2	25		T3	12
valid_sources[0x08]	9578	1			T1	5		T2	21		T3	16
valid_sources[0x09]	20161	1			T1	1		T2	16		T3	19
valid_sources[0x0a]	7404	1			T1	3		T2	24		T3	19
valid_sources[0x0b]	8709	1			T1	1		T2	26		T3	20
valid_sources[0x0c]	7502	1			T1	5		T2	19		T3	18
valid_sources[0x0d]	11983	1			T1	2		T2	22		T3	16
valid_sources[0x0e]	8648	1			T1	1		T2	18		T3	8
valid_sources[0x0f]	9817	1			T1	3		T2	18		T3	18
valid_sources[0x10]	11690	1			T1	2		T2	26		T3	18
valid_sources[0x11]	20115	1			T1	3		T2	12		T3	18
valid_sources[0x12]	7267	1			T1	2		T2	22		T3	19
valid_sources[0x13]	7331	1			T1	2		T2	15		T3	19
valid_sources[0x14]	10883	1			T1	4		T2	18		T3	16
valid_sources[0x15]	13933	1			T1	3		T2	13		T3	25
valid_sources[0x16]	8284	1			T1	3		T2	19		T3	13
valid_sources[0x17]	7376	1			T2	19		T3	10		T5	4
valid_sources[0x18]	12360	1			T2	24		T3	13		T5	1
valid_sources[0x19]	6906	1			T1	5		T2	22		T3	8
valid_sources[0x1a]	10332	1			T1	2		T2	24		T3	15
valid_sources[0x1b]	7025	1			T1	3		T2	20		T3	14
valid_sources[0x1c]	7843	1			T1	2		T2	21		T3	9
valid_sources[0x1d]	9547	1			T1	3		T2	16		T3	16
valid_sources[0x1e]	10497	1			T1	2		T2	17		T3	18
valid_sources[0x1f]	11369	1			T1	5		T2	21		T3	14
valid_sources[0x20]	7224	1			T1	5		T2	21		T3	17
valid_sources[0x21]	11445	1			T1	6		T2	11		T3	18
valid_sources[0x22]	12901	1			T1	3		T2	21		T3	10
valid_sources[0x23]	7188	1			T1	1		T2	31		T3	18
valid_sources[0x24]	7417	1			T1	2		T2	27		T3	13
valid_sources[0x25]	7498	1			T1	4		T2	20		T3	17
valid_sources[0x26]	7447	1			T1	6		T2	20		T3	7
valid_sources[0x27]	7919	1			T1	3		T2	21		T3	19
valid_sources[0x28]	7861	1			T2	26		T3	14		T5	3
valid_sources[0x29]	9654	1			T1	2		T2	33		T3	17
valid_sources[0x2a]	11539	1			T1	2		T2	16		T3	27
valid_sources[0x2b]	7384	1			T1	8		T2	23		T3	19
valid_sources[0x2c]	8581	1			T1	2		T2	16		T3	18
valid_sources[0x2d]	7648	1			T1	2		T2	21		T3	24
valid_sources[0x2e]	7573	1			T2	26		T3	11		T5	1
valid_sources[0x2f]	8015	1			T1	1		T2	20		T3	16
valid_sources[0x30]	6727	1			T1	4		T2	29		T3	15
valid_sources[0x31]	7232	1			T2	24		T3	15		T5	3
valid_sources[0x32]	9141	1			T1	2		T2	18		T3	19
valid_sources[0x33]	7265	1			T1	5		T2	20		T3	23
valid_sources[0x34]	7649	1			T1	5		T2	15		T3	13
valid_sources[0x35]	7841	1			T1	3		T2	28		T3	22
valid_sources[0x36]	7780	1			T1	5		T2	13		T3	35
valid_sources[0x37]	7396	1			T1	4		T2	16		T3	16
valid_sources[0x38]	7462	1			T1	1		T2	14		T3	13
valid_sources[0x39]	8562	1			T1	5		T2	31		T3	19
valid_sources[0x3a]	7546	1			T1	1		T2	16		T3	17
valid_sources[0x3b]	11616	1			T1	3		T2	12		T3	16
valid_sources[0x3c]	20275	1			T1	3		T2	15		T3	19
valid_sources[0x3d]	7432	1			T1	2		T2	22		T3	16
valid_sources[0x3e]	20377	1			T2	15		T3	18		T5	5
valid_sources[0x3f]	7453	1			T1	3		T2	21		T3	14
valid_sources[0x40]	13917	1			T1	3		T2	25		T3	9
valid_sources[0x41]	7315	1			T1	3		T2	24		T3	15
valid_sources[0x42]	14192	1			T1	2		T2	18		T3	21
valid_sources[0x43]	9298	1			T1	1		T2	27		T3	20
valid_sources[0x44]	7290	1			T1	4		T2	29		T3	11
valid_sources[0x45]	15786	1			T1	3		T2	20		T3	13
valid_sources[0x46]	9545	1			T1	4		T2	16		T3	20
valid_sources[0x47]	7079	1			T1	4		T2	30		T3	12
valid_sources[0x48]	7146	1			T1	6		T2	25		T3	14
valid_sources[0x49]	8456	1			T2	30		T3	20		T5	3
valid_sources[0x4a]	11688	1			T1	2		T2	25		T3	27
valid_sources[0x4b]	7476	1			T1	3		T2	23		T3	29
valid_sources[0x4c]	11449	1			T1	3		T2	20		T3	17
valid_sources[0x4d]	8426	1			T1	2		T2	17		T3	15
valid_sources[0x4e]	12621	1			T1	3		T2	20		T3	21
valid_sources[0x4f]	16205	1			T1	1		T2	26		T3	10
valid_sources[0x50]	7260	1			T2	44		T3	10		T5	3
valid_sources[0x51]	7071	1			T2	25		T3	18		T5	4
valid_sources[0x52]	11430	1			T1	3		T2	18		T3	7
valid_sources[0x53]	7144	1			T1	2		T2	14		T3	18
valid_sources[0x54]	12004	1			T1	3		T2	19		T3	17
valid_sources[0x55]	7282	1			T1	4		T2	28		T3	15
valid_sources[0x56]	7508	1			T1	1		T2	12		T3	15
valid_sources[0x57]	7444	1			T1	3		T2	18		T3	16
valid_sources[0x58]	8114	1			T1	4		T2	22		T3	22
valid_sources[0x59]	7317	1			T1	2		T2	25		T3	19
valid_sources[0x5a]	7361	1			T1	1		T2	21		T3	8
valid_sources[0x5b]	7163	1			T1	2		T2	19		T3	13
valid_sources[0x5c]	8623	1			T2	16		T3	18		T5	5
valid_sources[0x5d]	7255	1			T1	2		T2	17		T3	19
valid_sources[0x5e]	7378	1			T1	1		T2	21		T3	22
valid_sources[0x5f]	11807	1			T1	3		T2	13		T3	11
valid_sources[0x60]	7120	1			T1	2		T2	22		T3	12
valid_sources[0x61]	7230	1			T1	4		T2	21		T3	21
valid_sources[0x62]	13219	1			T1	2		T2	18		T3	13
valid_sources[0x63]	7282	1			T1	5		T2	24		T3	14
valid_sources[0x64]	8562	1			T1	3		T2	12		T3	19
valid_sources[0x65]	7530	1			T1	4		T2	14		T3	18
valid_sources[0x66]	9053	1			T1	1		T2	21		T3	8
valid_sources[0x67]	7427	1			T1	2		T2	19		T3	16
valid_sources[0x68]	7058	1			T1	1		T2	22		T3	16
valid_sources[0x69]	8248	1			T1	5		T2	21		T3	10
valid_sources[0x6a]	7025	1			T1	2		T2	17		T3	24
valid_sources[0x6b]	7082	1			T1	5		T2	22		T3	11
valid_sources[0x6c]	7381	1			T1	2		T2	20		T3	20
valid_sources[0x6d]	7770	1			T1	3		T2	16		T3	23
valid_sources[0x6e]	9648	1			T1	4		T2	27		T3	19
valid_sources[0x6f]	7591	1			T1	7		T2	24		T3	16
valid_sources[0x70]	7534	1			T1	4		T2	32		T3	11
valid_sources[0x71]	15728	1			T1	7		T2	17		T3	17
valid_sources[0x72]	14721	1			T1	4		T2	22		T3	15
valid_sources[0x73]	9640	1			T2	24		T3	18		T5	4
valid_sources[0x74]	9209	1			T1	3		T2	17		T3	15
valid_sources[0x75]	11590	1			T2	15		T3	20		T5	2
valid_sources[0x76]	7466	1			T1	4		T2	21		T3	15
valid_sources[0x77]	7967	1			T1	3		T2	21		T3	16
valid_sources[0x78]	7503	1			T1	8		T2	16		T3	21
valid_sources[0x79]	11978	1			T1	2		T2	25		T3	19
valid_sources[0x7a]	7449	1			T1	3		T2	28		T3	21
valid_sources[0x7b]	7328	1			T1	2		T2	12		T3	20
valid_sources[0x7c]	7467	1			T1	2		T2	19		T3	14
valid_sources[0x7d]	8370	1			T1	7		T2	10		T3	14
valid_sources[0x7e]	7330	1			T1	1		T2	20		T3	14
valid_sources[0x7f]	7572	1			T1	8		T2	20		T3	22
valid_sources[0x80]	9949	1			T1	5		T2	26		T3	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1059332

1

T2

2429

T3

2035

T4

42

values[0x0]

all_enables

biggest_size

84535

1

T1

170

T2

131

T3

52

values[0x1]

all_enables

biggest_size

62283

1

T1

115

T2

97

T3

37