Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30428	1			T1	217		T2	24		T3	9
auto[PWRUP]	135	1			T5	1		T38	1		T40	1
auto[ONEST_0]	81	1			T1	1		T40	1		T29	3
auto[ONEST_021]	20	1			T42	2		T43	1		T193	1
auto[ONEST_1]	73	1			T38	2		T29	1		T79	1
auto[ONEST_DONE]	3	1			T194	2		T195	1		-	-
auto[LP_0]	140	1			T38	3		T40	1		T29	2
auto[LP_021]	30	1			T42	1		T43	2		T196	1
auto[LP_1]	126	1			T1	1		T38	1		T40	1
auto[LP_EVAL]	66	1			T5	1		T40	1		T29	2
auto[LP_SLP]	532	1			T1	3		T5	1		T38	13
auto[LP_PWRUP]	25	1			T38	1		T40	1		T29	1
auto[NP_0]	144	1			T1	2		T38	1		T29	4
auto[NP_021]	37	1			T38	1		T41	2		T43	1
auto[NP_1]	181	1			T1	1		T5	1		T38	6
auto[NP_EVAL]	34	1			T41	1		T194	2		T175	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T197

3

T198

1

T199

2

min

29930

1

T1

201

T2

24

T3

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29938	1			T1	201		T2	24		T3	9
pow[0x1]	10	1			T196	1		T33	1		T200	1
pow[0x2]	12	1			T41	1		T43	1		T193	1
pow[0x3]	33	1			T38	1		T157	1		T16	1
pow[0x4]	58	1			T38	1		T79	1		T42	1
pow[0x5]	132	1			T5	1		T38	2		T40	3
pow[0x6]	270	1			T1	5		T38	5		T40	3
pow[0x7]	577	1			T1	8		T5	1		T38	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

206

1

T1

2

T38

4

T40

4

min

29427

1

T1

197

T2

24

T3

9

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29427	1			T1	197		T2	24		T3	9
pow[0x4]	1	1			T96	1		-	-		-	-
pow[0x5]	4	1			T201	1		T202	1		T203	1
pow[0x7]	3	1			T30	1		T195	1		T204	1
pow[0x8]	3	1			T38	1		T198	1		T204	1
pow[0x9]	5	1			T205	1		T206	1		T207	1
pow[0xa]	13	1			T42	1		T208	1		T209	1
pow[0xb]	38	1			T1	1		T43	1		T30	1
pow[0xc]	80	1			T1	2		T38	1		T40	1
pow[0xd]	170	1			T1	2		T38	1		T40	1
pow[0xe]	291	1			T1	5		T38	2		T40	2
pow[0xf]	613	1			T1	6		T5	2		T38	5