Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2378	1			T1	6		T5	11		T27	6
auto[PWRUP]	129	1			T5	1		T28	1		T29	3
auto[ONEST_0]	91	1			T1	1		T40	1		T79	2
auto[ONEST_021]	10	1			T1	1		T193	1		T339	1
auto[ONEST_1]	89	1			T1	2		T5	1		T38	2
auto[ONEST_DONE]	4	1			T340	1		T313	1		T341	1
auto[LP_0]	130	1			T1	2		T29	3		T79	1
auto[LP_021]	27	1			T38	1		T29	1		T39	1
auto[LP_1]	154	1			T1	3		T38	2		T40	2
auto[LP_EVAL]	62	1			T1	1		T38	1		T40	1
auto[LP_SLP]	595	1			T1	6		T5	2		T38	10
auto[LP_PWRUP]	33	1			T41	1		T43	2		T157	1
auto[NP_0]	256	1			T1	1		T5	3		T27	2
auto[NP_021]	53	1			T1	1		T5	1		T38	1
auto[NP_1]	236	1			T1	3		T5	1		T27	2
auto[NP_EVAL]	24	1			T41	1		T30	1		T31	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

14

1

T79

1

T196

1

T342

1

min

2064

1

T1

7

T5

17

T27

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2079	1			T1	7		T5	17		T27	10
pow[0x1]	16	1			T29	1		T196	1		T194	1
pow[0x2]	22	1			T29	1		T157	2		T15	1
pow[0x3]	39	1			T38	1		T29	2		T42	1
pow[0x4]	79	1			T1	1		T29	1		T79	1
pow[0x5]	132	1			T38	1		T40	1		T39	1
pow[0x6]	274	1			T1	2		T38	2		T40	3
pow[0x7]	557	1			T1	10		T38	8		T40	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

209

1

T38

3

T40

1

T29

8

min

1409

1

T1

2

T5

13

T27

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1414	1			T1	2		T5	13		T27	6
pow[0x1]	15	1			T5	1		T33	7		T16	2
pow[0x2]	27	1			T29	2		T30	4		T31	3
pow[0x3]	56	1			T5	2		T27	1		T28	2
pow[0x4]	59	1			T27	3		T29	1		T31	1
pow[0x5]	2	1			T330	1		T343	1		-	-
pow[0x6]	1	1			T198	1		-	-		-	-
pow[0x8]	1	1			T1	1		-	-		-	-
pow[0x9]	6	1			T42	1		T193	1		T313	1
pow[0xa]	33	1			T16	1		T340	1		T194	1
pow[0xb]	38	1			T29	2		T42	4		T43	1
pow[0xc]	89	1			T29	2		T79	2		T42	2
pow[0xd]	146	1			T1	2		T38	2		T29	5
pow[0xe]	323	1			T1	2		T5	1		T38	3
pow[0xf]	629	1			T1	5		T5	2		T38	10