Unified Coverage Report :: Module

Module : adc_ctrl_intr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.00	100.00	96.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_adc_ctrl_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_adc_ctrl_intr_o	100.00	100.00	100.00			100.00	100.00
u_match_sync	93.75	100.00	75.00			100.00	100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_intr

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	39	1	1	100.00
ALWAYS	51	6	6	100.00
CONT_ASSIGN	64	1	1	100.00
ALWAYS	68	6	6	100.00
ALWAYS	95	6	6	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	119	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
			MISSING_ELSE
64	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
95	1	1
96	1	1
97	1	1
99	1	1
100	1	1
101	1	1
			MISSING_ELSE
106	1	1
111	1	1
112	1	1
113	1	1
115	1	1
119	1	1

Cond Coverage for Module : adc_ctrl_intr

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION ((aon_req_hold_q == '0) && ((|aon_staging_reqs_q)))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T29,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       64
 SUB-EXPRESSION (aon_req_hold_q == '0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       106
 EXPRESSION (cfg_intr_trans_en_i && dst_ack_q && req_hold_q[8])
             ---------1---------    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T8
1	0	1	Covered	T2,T27,T48
1	1	0	Covered	T2,T7,T11
1	1	1	Covered	T2,T27,T48

 LINE       115
 EXPRESSION (cfg_oneshot_done_i && cfg_oneshot_done_en_i)
             ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T5,T10
1	1	Covered	T4,T5,T9

Branch Coverage for Module : adc_ctrl_intr

	Line No.	Total	Covered	Percent
Branches		11	11	100.00
IF	51	4	4	100.00
IF	68	4	4	100.00
IF	95	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	51	if ((!rst_aon_ni))
-2-:	53	if (aon_ld_req)
-3-:	55	if ((|aon_reqs))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	68	if ((!rst_aon_ni))
-2-:	70	if (aon_ld_req)
-3-:	72	if (aon_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	95	if ((!rst_ni))
-2-:	100	if (dst_ack)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3