Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2486	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2689	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2616	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2725	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2561	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2615	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2700	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2812	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2728	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2651	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2661	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2588	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2600	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2659	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2623	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2864	0	0
adc_en_ctl_rd_A	2147483647	2202	0	0
adc_fsm_rst_rd_A	2147483647	2048	0	0
adc_intr_ctl_rd_A	2147483647	2645	0	0
adc_lp_sample_ctl_rd_A	2147483647	2182	0	0
adc_pd_ctl_rd_A	2147483647	2298	0	0
adc_sample_ctl_rd_A	2147483647	2128	0	0
adc_wakeup_ctl_rd_A	2147483647	2319	0	0
intr_enable_rd_A	2147483647	2597	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2486	0	0
T5	372290	40	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	36	0	0
T16	0	17	0	0
T17	0	16	0	0
T18	0	14	0	0
T19	0	2	0	0
T20	0	39	0	0
T21	0	45	0	0
T22	0	19	0	0
T23	0	30	0	0
T24	232200	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2689	0	0
T5	372290	37	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	32	0	0
T16	0	18	0	0
T17	0	26	0	0
T18	0	39	0	0
T19	0	2	0	0
T20	0	44	0	0
T21	0	27	0	0
T22	0	5	0	0
T24	232200	0	0	0
T25	0	10	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2616	0	0
T5	372290	35	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	54	0	0
T16	0	24	0	0
T17	0	24	0	0
T18	0	25	0	0
T19	0	1	0	0
T20	0	44	0	0
T21	0	30	0	0
T22	0	12	0	0
T24	232200	0	0	0
T25	0	8	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2725	0	0
T5	372290	55	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	27	0	0
T16	0	29	0	0
T17	0	19	0	0
T18	0	38	0	0
T20	0	45	0	0
T21	0	46	0	0
T22	0	8	0	0
T23	0	30	0	0
T24	232200	0	0	0
T25	0	14	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2561	0	0
T5	372290	55	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	39	0	0
T16	0	44	0	0
T17	0	16	0	0
T18	0	42	0	0
T19	0	3	0	0
T20	0	36	0	0
T21	0	34	0	0
T22	0	6	0	0
T24	232200	0	0	0
T25	0	4	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2615	0	0
T5	372290	24	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	38	0	0
T16	0	12	0	0
T17	0	20	0	0
T18	0	28	0	0
T19	0	16	0	0
T20	0	28	0	0
T21	0	39	0	0
T23	0	23	0	0
T24	232200	0	0	0
T25	0	10	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2700	0	0
T5	372290	34	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	31	0	0
T16	0	15	0	0
T17	0	27	0	0
T18	0	29	0	0
T19	0	9	0	0
T20	0	20	0	0
T21	0	44	0	0
T22	0	10	0	0
T24	232200	0	0	0
T25	0	20	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2812	0	0
T5	372290	41	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	35	0	0
T16	0	24	0	0
T17	0	16	0	0
T18	0	46	0	0
T19	0	8	0	0
T20	0	38	0	0
T21	0	21	0	0
T22	0	14	0	0
T24	232200	0	0	0
T25	0	10	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2728	0	0
T5	372290	28	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	30	0	0
T16	0	24	0	0
T17	0	20	0	0
T18	0	52	0	0
T19	0	14	0	0
T20	0	29	0	0
T21	0	39	0	0
T22	0	1	0	0
T24	232200	0	0	0
T25	0	4	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2651	0	0
T5	372290	50	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	48	0	0
T16	0	16	0	0
T17	0	8	0	0
T18	0	24	0	0
T19	0	3	0	0
T20	0	33	0	0
T21	0	17	0	0
T22	0	14	0	0
T24	232200	0	0	0
T25	0	22	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2661	0	0
T5	372290	36	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	37	0	0
T16	0	24	0	0
T17	0	19	0	0
T18	0	23	0	0
T19	0	10	0	0
T20	0	42	0	0
T21	0	16	0	0
T22	0	15	0	0
T24	232200	0	0	0
T25	0	11	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2588	0	0
T5	372290	38	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	21	0	0
T16	0	4	0	0
T17	0	15	0	0
T18	0	42	0	0
T19	0	8	0	0
T20	0	40	0	0
T21	0	26	0	0
T22	0	2	0	0
T24	232200	0	0	0
T25	0	7	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2600	0	0
T5	372290	37	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	31	0	0
T16	0	10	0	0
T17	0	4	0	0
T18	0	34	0	0
T19	0	9	0	0
T20	0	39	0	0
T21	0	32	0	0
T22	0	7	0	0
T24	232200	0	0	0
T25	0	15	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2659	0	0
T5	372290	38	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	30	0	0
T16	0	9	0	0
T17	0	17	0	0
T18	0	43	0	0
T20	0	35	0	0
T21	0	20	0	0
T22	0	4	0	0
T23	0	44	0	0
T24	232200	0	0	0
T25	0	11	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2623	0	0
T5	372290	33	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	35	0	0
T16	0	31	0	0
T17	0	39	0	0
T18	0	46	0	0
T19	0	12	0	0
T20	0	29	0	0
T21	0	21	0	0
T22	0	13	0	0
T24	232200	0	0	0
T25	0	6	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2864	0	0
T5	372290	58	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	34	0	0
T16	0	30	0	0
T17	0	7	0	0
T18	0	38	0	0
T19	0	15	0	0
T20	0	23	0	0
T21	0	28	0	0
T23	0	42	0	0
T24	232200	0	0	0
T25	0	15	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2202	0	0
T5	372290	34	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	47	0	0
T16	0	22	0	0
T17	0	18	0	0
T18	0	43	0	0
T19	0	20	0	0
T20	0	36	0	0
T21	0	23	0	0
T22	0	15	0	0
T24	232200	0	0	0
T25	0	15	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2048	0	0
T5	372290	27	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	34	0	0
T16	0	23	0	0
T17	0	38	0	0
T18	0	42	0	0
T19	0	12	0	0
T20	0	34	0	0
T21	0	17	0	0
T22	0	17	0	0
T24	232200	0	0	0
T25	0	4	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2645	0	0
T5	372290	45	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	28	0	0
T16	0	20	0	0
T17	0	20	0	0
T18	0	35	0	0
T19	0	27	0	0
T20	0	41	0	0
T21	0	43	0	0
T22	0	9	0	0
T24	232200	0	0	0
T25	0	10	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2182	0	0
T5	372290	28	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	35	0	0
T16	0	19	0	0
T17	0	33	0	0
T18	0	31	0	0
T19	0	24	0	0
T20	0	33	0	0
T21	0	34	0	0
T23	0	41	0	0
T24	232200	0	0	0
T25	0	10	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2298	0	0
T5	372290	28	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	29	0	0
T16	0	31	0	0
T17	0	28	0	0
T18	0	33	0	0
T19	0	9	0	0
T20	0	47	0	0
T21	0	38	0	0
T22	0	8	0	0
T24	232200	0	0	0
T25	0	15	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2128	0	0
T5	372290	40	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	42	0	0
T16	0	30	0	0
T17	0	17	0	0
T18	0	47	0	0
T19	0	5	0	0
T20	0	43	0	0
T21	0	33	0	0
T22	0	9	0	0
T24	232200	0	0	0
T25	0	26	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2319	0	0
T5	372290	55	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	35	0	0
T16	0	7	0	0
T17	0	10	0	0
T18	0	25	0	0
T19	0	15	0	0
T20	0	34	0	0
T21	0	48	0	0
T22	0	15	0	0
T24	232200	0	0	0
T25	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2597	0	0
T5	372290	17	0	0
T6	949101	0	0	0
T7	411842	0	0	0
T8	453536	0	0	0
T9	153321	0	0	0
T10	282416	0	0	0
T11	193938	0	0	0
T12	316116	0	0	0
T13	669300	0	0	0
T15	0	31	0	0
T16	0	56	0	0
T17	0	24	0	0
T18	0	25	0	0
T19	0	21	0	0
T20	0	36	0	0
T21	0	75	0	0
T24	232200	0	0	0
T25	0	28	0	0
T26	0	8	0	0