Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1184032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1161939

1

T1

58

T2

4350

T3

1381

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2050496	1			T1	81		T2	8261		T3	2487
values[0x0]	147362	1			T1	32		T2	285		T3	138
values[0x1]	148113	1			T1	31		T2	256		T3	169

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	947719	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1398252

1

T1

73

T2

5231

T3

1685

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7824	1			T2	22		T6	7		T8	4
valid_sources[0x01]	6760	1			T2	32		T5	20		T6	3
valid_sources[0x02]	6773	1			T2	21		T5	17		T6	10
valid_sources[0x03]	7903	1			T2	41		T3	11		T6	5
valid_sources[0x04]	8498	1			T2	32		T5	30		T6	4
valid_sources[0x05]	6210	1			T2	30		T5	5		T6	5
valid_sources[0x06]	6552	1			T2	39		T5	6		T6	2
valid_sources[0x07]	6841	1			T2	39		T5	17		T6	4
valid_sources[0x08]	7289	1			T2	32		T5	4		T6	4
valid_sources[0x09]	10837	1			T2	39		T3	9		T5	16
valid_sources[0x0a]	8870	1			T2	25		T5	16		T6	3
valid_sources[0x0b]	6804	1			T2	40		T5	21		T6	1
valid_sources[0x0c]	9342	1			T2	27		T5	6		T6	3
valid_sources[0x0d]	6619	1			T2	21		T6	3		T8	3
valid_sources[0x0e]	7850	1			T2	42		T6	3		T8	2
valid_sources[0x0f]	6897	1			T2	24		T5	1		T6	5
valid_sources[0x10]	7517	1			T2	36		T6	6		T8	4
valid_sources[0x11]	7019	1			T2	31		T3	45		T6	2
valid_sources[0x12]	7618	1			T2	32		T5	11		T6	4
valid_sources[0x13]	23331	1			T2	30		T3	69		T5	11
valid_sources[0x14]	6662	1			T2	25		T5	16		T6	2
valid_sources[0x15]	7216	1			T2	27		T5	11		T6	3
valid_sources[0x16]	9057	1			T2	23		T5	22		T6	5
valid_sources[0x17]	9902	1			T2	28		T5	11		T6	2
valid_sources[0x18]	14225	1			T2	23		T5	2		T6	6
valid_sources[0x19]	7237	1			T2	42		T3	10		T5	2
valid_sources[0x1a]	6559	1			T2	22		T6	1		T8	2
valid_sources[0x1b]	7660	1			T2	34		T5	18		T6	4
valid_sources[0x1c]	11132	1			T2	30		T5	7		T6	3
valid_sources[0x1d]	14274	1			T1	144		T2	43		T5	6
valid_sources[0x1e]	6899	1			T2	35		T5	7		T6	3
valid_sources[0x1f]	11712	1			T2	20		T5	28		T6	4
valid_sources[0x20]	6698	1			T2	45		T5	6		T6	4
valid_sources[0x21]	9522	1			T2	29		T5	7		T6	5
valid_sources[0x22]	7178	1			T2	35		T6	4		T8	5
valid_sources[0x23]	7677	1			T2	24		T6	3		T11	4
valid_sources[0x24]	7348	1			T2	31		T3	44		T5	18
valid_sources[0x25]	7477	1			T2	49		T5	1		T6	5
valid_sources[0x26]	11228	1			T2	39		T5	10		T6	4
valid_sources[0x27]	10047	1			T2	24		T3	97		T6	4
valid_sources[0x28]	9221	1			T2	47		T3	939		T6	2
valid_sources[0x29]	6934	1			T2	26		T5	34		T6	4
valid_sources[0x2a]	6517	1			T2	22		T5	8		T8	2
valid_sources[0x2b]	6767	1			T2	50		T6	4		T8	3
valid_sources[0x2c]	6657	1			T2	34		T5	26		T6	2
valid_sources[0x2d]	7322	1			T2	29		T5	12		T6	4
valid_sources[0x2e]	7142	1			T2	29		T3	52		T5	3
valid_sources[0x2f]	8572	1			T2	46		T5	8		T6	2
valid_sources[0x30]	9633	1			T2	39		T5	20		T6	2
valid_sources[0x31]	6879	1			T2	57		T6	2		T8	3
valid_sources[0x32]	7481	1			T2	27		T5	7		T6	1
valid_sources[0x33]	6525	1			T2	28		T3	1		T5	5
valid_sources[0x34]	6960	1			T2	30		T5	22		T6	4
valid_sources[0x35]	11226	1			T2	20		T5	3		T6	4
valid_sources[0x36]	8402	1			T2	17		T5	7		T6	3
valid_sources[0x37]	8520	1			T2	41		T5	2		T6	3
valid_sources[0x38]	6669	1			T2	27		T3	3		T5	12
valid_sources[0x39]	6979	1			T2	19		T5	1		T6	1
valid_sources[0x3a]	10432	1			T2	38		T5	1		T6	2
valid_sources[0x3b]	6957	1			T2	39		T6	3		T8	4
valid_sources[0x3c]	7041	1			T2	26		T5	16		T6	6
valid_sources[0x3d]	7369	1			T2	48		T5	16		T6	4
valid_sources[0x3e]	13387	1			T2	5		T6	3		T11	6
valid_sources[0x3f]	8805	1			T2	30		T5	5		T6	1
valid_sources[0x40]	14336	1			T2	45		T5	3		T6	1
valid_sources[0x41]	6962	1			T2	62		T5	3		T6	1
valid_sources[0x42]	6920	1			T2	41		T5	13		T6	5
valid_sources[0x43]	7535	1			T2	34		T5	2		T6	1
valid_sources[0x44]	6566	1			T2	19		T5	4		T6	4
valid_sources[0x45]	7153	1			T2	50		T7	2		T8	3
valid_sources[0x46]	6689	1			T2	23		T3	9		T5	9
valid_sources[0x47]	7888	1			T2	41		T6	3		T8	6
valid_sources[0x48]	10860	1			T2	37		T5	6		T6	1
valid_sources[0x49]	7022	1			T2	19		T5	3		T6	4
valid_sources[0x4a]	6777	1			T2	36		T5	3		T6	3
valid_sources[0x4b]	6774	1			T2	33		T5	8		T6	3
valid_sources[0x4c]	8597	1			T2	29		T3	15		T5	5
valid_sources[0x4d]	7592	1			T2	58		T5	21		T6	3
valid_sources[0x4e]	6992	1			T2	63		T6	1		T8	6
valid_sources[0x4f]	11515	1			T2	25		T6	8		T8	4
valid_sources[0x50]	11104	1			T2	17		T5	18		T8	4
valid_sources[0x51]	9869	1			T2	34		T5	19		T6	2
valid_sources[0x52]	6606	1			T2	21		T6	5		T8	7
valid_sources[0x53]	7064	1			T2	40		T5	2		T6	5
valid_sources[0x54]	11204	1			T2	18		T5	1		T6	3
valid_sources[0x55]	14966	1			T2	31		T5	13		T6	4
valid_sources[0x56]	9282	1			T2	10		T5	14		T6	6
valid_sources[0x57]	7116	1			T2	38		T3	19		T5	4
valid_sources[0x58]	6973	1			T2	34		T6	5		T10	2
valid_sources[0x59]	10025	1			T2	31		T5	4		T6	7
valid_sources[0x5a]	9377	1			T2	43		T5	5		T6	4
valid_sources[0x5b]	11270	1			T2	42		T5	15		T6	6
valid_sources[0x5c]	6694	1			T2	37		T6	6		T8	10
valid_sources[0x5d]	8189	1			T2	39		T6	1		T8	4
valid_sources[0x5e]	8181	1			T2	22		T6	3		T8	5
valid_sources[0x5f]	6666	1			T2	37		T6	7		T8	5
valid_sources[0x60]	8715	1			T2	38		T3	3		T5	5
valid_sources[0x61]	6744	1			T2	28		T5	1		T6	1
valid_sources[0x62]	11030	1			T2	52		T5	22		T6	1
valid_sources[0x63]	6835	1			T2	15		T6	3		T8	5
valid_sources[0x64]	9088	1			T2	42		T3	934		T5	21
valid_sources[0x65]	6982	1			T2	31		T5	12		T6	3
valid_sources[0x66]	6717	1			T2	46		T5	4		T6	6
valid_sources[0x67]	9161	1			T2	14		T6	7		T8	5
valid_sources[0x68]	7935	1			T2	22		T3	1		T6	5
valid_sources[0x69]	6571	1			T2	18		T6	1		T8	5
valid_sources[0x6a]	9496	1			T2	27		T5	7		T6	4
valid_sources[0x6b]	8772	1			T2	36		T5	8		T6	4
valid_sources[0x6c]	11314	1			T2	18		T5	3		T6	4
valid_sources[0x6d]	11359	1			T2	28		T6	5		T8	3
valid_sources[0x6e]	13698	1			T2	33		T3	29		T5	33
valid_sources[0x6f]	7631	1			T2	53		T5	16		T6	4
valid_sources[0x70]	6335	1			T2	26		T5	7		T6	4
valid_sources[0x71]	11381	1			T2	52		T5	20		T6	4
valid_sources[0x72]	6642	1			T2	48		T6	3		T8	3
valid_sources[0x73]	11028	1			T2	46		T6	7		T8	1
valid_sources[0x74]	25175	1			T2	32		T6	4		T8	4
valid_sources[0x75]	7688	1			T2	41		T6	5		T8	1
valid_sources[0x76]	14735	1			T2	50		T6	2		T8	5
valid_sources[0x77]	9601	1			T2	41		T5	5		T6	4
valid_sources[0x78]	8886	1			T2	42		T5	7		T6	3
valid_sources[0x79]	6913	1			T2	22		T5	4		T6	4
valid_sources[0x7a]	8077	1			T2	36		T5	5		T6	9
valid_sources[0x7b]	11298	1			T2	44		T5	3		T6	3
valid_sources[0x7c]	10591	1			T2	25		T5	8		T6	3
valid_sources[0x7d]	10708	1			T2	30		T6	2		T8	2
valid_sources[0x7e]	14127	1			T2	41		T5	7		T6	9
valid_sources[0x7f]	6392	1			T2	41		T5	21		T6	2
valid_sources[0x80]	11493	1			T2	29		T6	2		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1021846

1

T1

35

T2

4130

T3

1222

values[0x0]

all_enables

biggest_size

81352

1

T1

18

T2

147

T3

90

values[0x1]

all_enables

biggest_size

58741

1

T1

5

T2

73

T3

69