Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
84.44	84.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	84.44	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	7	38	84.44

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29604	1			T2	16		T3	26		T4	199
auto[PWRUP]	111	1			T4	2		T44	3		T17	2
auto[ONEST_0]	68	1			T44	2		T48	2		T217	1
auto[ONEST_021]	15	1			T48	1		T218	1		T219	1
auto[ONEST_1]	72	1			T44	1		T17	4		T45	3
auto[ONEST_DONE]	2	1			T51	1		T220	1		-	-
auto[LP_0]	113	1			T4	1		T44	3		T17	1
auto[LP_021]	31	1			T17	1		T166	1		T179	2
auto[LP_1]	131	1			T4	2		T44	1		T17	2
auto[LP_EVAL]	69	1			T4	2		T44	1		T17	2
auto[LP_SLP]	521	1			T4	3		T44	5		T17	8
auto[LP_PWRUP]	28	1			T47	1		T48	1		T51	2
auto[NP_0]	138	1			T4	2		T44	1		T17	2
auto[NP_021]	29	1			T44	2		T17	1		T221	1
auto[NP_1]	139	1			T44	1		T17	1		T45	1
auto[NP_EVAL]	43	1			T4	1		T45	1		T47	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T45

1

T50

1

T219

1

min

29145

1

T2

16

T3

26

T4

190

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29153	1			T2	16		T3	26		T4	190
pow[0x1]	12	1			T44	1		T51	1		T20	1
pow[0x2]	18	1			T44	1		T51	1		T217	2
pow[0x3]	31	1			T17	3		T45	1		T47	1
pow[0x4]	61	1			T4	1		T44	1		T17	1
pow[0x5]	113	1			T4	1		T44	2		T17	4
pow[0x6]	253	1			T4	5		T44	3		T17	2
pow[0x7]	479	1			T4	7		T44	7		T17	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

169

1

T4

3

T44

2

T17

6

min

28642

1

T2

16

T3

26

T4

184

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28642	1			T2	16		T3	26		T4	184
pow[0x7]	1	1			T222	1		-	-		-	-
pow[0x8]	2	1			T166	1		T223	1		-	-
pow[0x9]	6	1			T224	1		T25	1		T225	1
pow[0xa]	18	1			T45	1		T47	2		T226	1
pow[0xb]	39	1			T17	1		T19	1		T51	1
pow[0xc]	67	1			T4	1		T17	1		T47	2
pow[0xd]	140	1			T44	1		T45	2		T47	1
pow[0xe]	262	1			T4	5		T44	2		T17	3
pow[0xf]	623	1			T4	7		T44	15		T17	9