Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2382	1			T4	13		T44	17		T42	5
auto[PWRUP]	121	1			T4	3		T44	4		T17	1
auto[ONEST_0]	69	1			T4	2		T16	1		T17	1
auto[ONEST_021]	20	1			T47	1		T51	1		T82	1
auto[ONEST_1]	90	1			T4	1		T44	3		T17	1
auto[ONEST_DONE]	1	1			T350	1		-	-		-	-
auto[LP_0]	122	1			T44	1		T17	3		T45	3
auto[LP_021]	36	1			T16	1		T17	2		T47	1
auto[LP_1]	145	1			T4	1		T44	1		T17	1
auto[LP_EVAL]	69	1			T4	1		T17	1		T45	1
auto[LP_SLP]	472	1			T4	6		T44	8		T16	2
auto[LP_PWRUP]	37	1			T4	2		T20	1		T221	1
auto[NP_0]	220	1			T4	3		T44	3		T16	5
auto[NP_021]	59	1			T4	2		T44	1		T17	3
auto[NP_1]	231	1			T4	2		T44	2		T16	1
auto[NP_EVAL]	28	1			T4	1		T17	1		T36	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T19

1

T351

1

T286

2

min

1943

1

T4

8

T44

10

T42

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1961	1			T4	8		T44	10		T42	5
pow[0x1]	6	1			T17	2		T35	1		T276	1
pow[0x2]	22	1			T4	1		T44	1		T19	1
pow[0x3]	46	1			T17	1		T45	1		T48	2
pow[0x4]	72	1			T4	1		T44	1		T17	2
pow[0x5]	138	1			T4	4		T44	2		T17	3
pow[0x6]	242	1			T4	6		T44	5		T17	5
pow[0x7]	527	1			T4	6		T44	8		T16	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

191

1

T4

2

T44

6

T17

2

min

1375

1

T4

4

T44

5

T42

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1377	1			T4	4		T44	5		T42	5
pow[0x1]	24	1			T20	2		T23	6		T314	1
pow[0x2]	33	1			T17	3		T36	1		T246	2
pow[0x3]	42	1			T35	6		T36	1		T19	5
pow[0x4]	64	1			T16	5		T36	1		T20	1
pow[0x5]	2	1			T352	1		T353	1		-	-
pow[0x6]	3	1			T354	1		T220	1		T243	1
pow[0x7]	4	1			T17	1		T355	1		T356	1
pow[0x8]	5	1			T246	1		T118	1		T357	1
pow[0x9]	16	1			T17	1		T166	1		T179	1
pow[0xa]	17	1			T4	1		T166	1		T222	1
pow[0xb]	37	1			T17	1		T47	2		T48	1
pow[0xc]	93	1			T17	3		T45	2		T48	1
pow[0xd]	152	1			T4	1		T44	3		T16	1
pow[0xe]	280	1			T4	5		T44	3		T16	1
pow[0xf]	626	1			T4	10		T44	8		T17	5