Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2392	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2471	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2347	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2495	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2403	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2475	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2641	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2518	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2404	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2597	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2648	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2534	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2371	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2569	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2418	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2472	0	0
adc_en_ctl_rd_A	2147483647	2217	0	0
adc_fsm_rst_rd_A	2147483647	1979	0	0
adc_intr_ctl_rd_A	2147483647	2418	0	0
adc_lp_sample_ctl_rd_A	2147483647	2061	0	0
adc_pd_ctl_rd_A	2147483647	2440	0	0
adc_sample_ctl_rd_A	2147483647	1872	0	0
adc_wakeup_ctl_rd_A	2147483647	2282	0	0
intr_enable_rd_A	2147483647	2424	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2392	0	0
T16	423787	47	0	0
T17	110864	26	0	0
T18	0	5	0	0
T19	0	45	0	0
T20	0	33	0	0
T21	0	20	0	0
T22	0	16	0	0
T23	0	44	0	0
T24	0	11	0	0
T25	0	15	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2471	0	0
T16	423787	45	0	0
T17	110864	17	0	0
T18	0	15	0	0
T19	0	45	0	0
T20	0	33	0	0
T21	0	16	0	0
T22	0	27	0	0
T23	0	36	0	0
T24	0	22	0	0
T25	0	19	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2347	0	0
T16	423787	52	0	0
T17	110864	31	0	0
T18	0	10	0	0
T19	0	40	0	0
T20	0	39	0	0
T21	0	19	0	0
T22	0	13	0	0
T23	0	45	0	0
T24	0	13	0	0
T25	0	6	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2495	0	0
T16	423787	21	0	0
T17	110864	31	0	0
T18	0	21	0	0
T19	0	25	0	0
T20	0	29	0	0
T21	0	6	0	0
T22	0	7	0	0
T23	0	29	0	0
T24	0	18	0	0
T25	0	16	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2403	0	0
T16	423787	51	0	0
T17	110864	18	0	0
T18	0	9	0	0
T19	0	36	0	0
T20	0	41	0	0
T21	0	16	0	0
T22	0	14	0	0
T23	0	61	0	0
T24	0	24	0	0
T25	0	15	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2475	0	0
T16	423787	49	0	0
T17	110864	22	0	0
T18	0	10	0	0
T19	0	37	0	0
T20	0	30	0	0
T21	0	12	0	0
T22	0	6	0	0
T23	0	44	0	0
T24	0	18	0	0
T25	0	24	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2641	0	0
T16	423787	30	0	0
T17	110864	23	0	0
T18	0	28	0	0
T19	0	34	0	0
T20	0	26	0	0
T21	0	12	0	0
T22	0	10	0	0
T23	0	38	0	0
T24	0	24	0	0
T25	0	12	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2518	0	0
T16	423787	42	0	0
T17	110864	20	0	0
T18	0	16	0	0
T19	0	42	0	0
T20	0	31	0	0
T21	0	12	0	0
T22	0	11	0	0
T23	0	30	0	0
T24	0	15	0	0
T25	0	9	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2404	0	0
T16	423787	24	0	0
T17	110864	37	0	0
T18	0	8	0	0
T19	0	41	0	0
T20	0	40	0	0
T21	0	4	0	0
T22	0	12	0	0
T23	0	27	0	0
T24	0	23	0	0
T25	0	16	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2597	0	0
T16	423787	36	0	0
T17	110864	34	0	0
T18	0	14	0	0
T19	0	44	0	0
T20	0	31	0	0
T21	0	8	0	0
T22	0	18	0	0
T23	0	26	0	0
T24	0	20	0	0
T25	0	25	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2648	0	0
T16	423787	54	0	0
T17	110864	10	0	0
T18	0	11	0	0
T19	0	20	0	0
T20	0	31	0	0
T21	0	13	0	0
T22	0	18	0	0
T23	0	33	0	0
T24	0	25	0	0
T25	0	14	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2534	0	0
T16	423787	37	0	0
T17	110864	12	0	0
T18	0	16	0	0
T19	0	41	0	0
T20	0	27	0	0
T21	0	11	0	0
T22	0	8	0	0
T23	0	44	0	0
T24	0	17	0	0
T25	0	11	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2371	0	0
T16	423787	28	0	0
T17	110864	18	0	0
T18	0	13	0	0
T19	0	51	0	0
T20	0	26	0	0
T21	0	8	0	0
T22	0	17	0	0
T23	0	37	0	0
T24	0	11	0	0
T25	0	24	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2569	0	0
T16	423787	35	0	0
T17	110864	22	0	0
T18	0	19	0	0
T19	0	23	0	0
T20	0	36	0	0
T21	0	18	0	0
T22	0	14	0	0
T23	0	55	0	0
T24	0	19	0	0
T25	0	14	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2418	0	0
T16	423787	43	0	0
T17	110864	19	0	0
T18	0	16	0	0
T19	0	46	0	0
T20	0	25	0	0
T21	0	12	0	0
T22	0	7	0	0
T23	0	35	0	0
T24	0	11	0	0
T25	0	7	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2472	0	0
T16	423787	52	0	0
T17	110864	12	0	0
T18	0	14	0	0
T19	0	33	0	0
T20	0	17	0	0
T21	0	12	0	0
T22	0	8	0	0
T23	0	36	0	0
T24	0	14	0	0
T25	0	16	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2217	0	0
T16	423787	43	0	0
T17	110864	10	0	0
T18	0	21	0	0
T19	0	46	0	0
T20	0	21	0	0
T21	0	13	0	0
T22	0	15	0	0
T23	0	25	0	0
T24	0	24	0	0
T25	0	15	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1979	0	0
T16	423787	42	0	0
T17	110864	20	0	0
T18	0	16	0	0
T19	0	23	0	0
T20	0	36	0	0
T21	0	14	0	0
T22	0	24	0	0
T23	0	22	0	0
T24	0	23	0	0
T25	0	22	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2418	0	0
T16	423787	38	0	0
T17	110864	29	0	0
T18	0	15	0	0
T19	0	43	0	0
T20	0	27	0	0
T21	0	15	0	0
T22	0	18	0	0
T23	0	35	0	0
T24	0	20	0	0
T25	0	6	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2061	0	0
T16	423787	30	0	0
T17	110864	33	0	0
T18	0	11	0	0
T19	0	33	0	0
T20	0	29	0	0
T21	0	1	0	0
T22	0	15	0	0
T23	0	53	0	0
T24	0	34	0	0
T25	0	26	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2440	0	0
T16	423787	47	0	0
T17	110864	14	0	0
T18	0	18	0	0
T19	0	39	0	0
T20	0	30	0	0
T21	0	15	0	0
T22	0	12	0	0
T23	0	23	0	0
T24	0	32	0	0
T25	0	21	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1872	0	0
T16	423787	33	0	0
T17	110864	17	0	0
T18	0	9	0	0
T19	0	43	0	0
T20	0	44	0	0
T21	0	6	0	0
T22	0	9	0	0
T23	0	37	0	0
T24	0	47	0	0
T25	0	5	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2282	0	0
T16	423787	27	0	0
T17	110864	24	0	0
T18	0	5	0	0
T19	0	40	0	0
T20	0	34	0	0
T21	0	13	0	0
T22	0	22	0	0
T23	0	14	0	0
T24	0	20	0	0
T25	0	12	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2424	0	0
T16	423787	24	0	0
T17	110864	46	0	0
T18	0	5	0	0
T19	0	53	0	0
T20	0	75	0	0
T21	0	15	0	0
T22	0	15	0	0
T23	0	35	0	0
T24	0	6	0	0
T26	599097	0	0	0
T27	303798	0	0	0
T28	782007	0	0	0
T29	483146	0	0	0
T30	629766	0	0	0
T31	346470	0	0	0
T32	295888	0	0	0
T33	852812	0	0	0
T34	0	7	0	0