Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1190336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1164740

1

T1

1418

T2

35

T3

954

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2060775	1			T1	2513		T3	1680		T4	81
values[0x0]	146419	1			T1	164		T2	23		T3	116
values[0x1]	147882	1			T1	154		T2	38		T3	103

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	953487	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1401589

1

T1

1723

T2

36

T3

1136

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11779	1			T1	8		T6	36		T7	42
valid_sources[0x01]	6929	1			T1	4		T6	27		T7	36
valid_sources[0x02]	9229	1			T2	2		T3	11		T6	13
valid_sources[0x03]	6536	1			T1	5		T3	1		T6	14
valid_sources[0x04]	7037	1			T1	3		T3	25		T6	12
valid_sources[0x05]	7611	1			T1	9		T3	2		T6	18
valid_sources[0x06]	6726	1			T1	4		T2	6		T3	2
valid_sources[0x07]	7902	1			T1	18		T3	5		T6	13
valid_sources[0x08]	9708	1			T1	5		T2	2		T3	1
valid_sources[0x09]	6719	1			T1	8		T3	1		T6	25
valid_sources[0x0a]	7714	1			T1	14		T3	10		T6	17
valid_sources[0x0b]	6867	1			T1	6		T3	4		T6	13
valid_sources[0x0c]	6951	1			T1	2		T3	8		T6	21
valid_sources[0x0d]	6999	1			T1	1		T3	2		T6	17
valid_sources[0x0e]	6652	1			T1	4		T6	16		T7	34
valid_sources[0x0f]	6707	1			T1	7		T3	9		T6	33
valid_sources[0x10]	7824	1			T1	30		T3	7		T6	11
valid_sources[0x11]	11384	1			T1	5		T2	2		T3	2
valid_sources[0x12]	9862	1			T1	12		T3	4		T6	12
valid_sources[0x13]	6624	1			T1	9		T3	6		T6	28
valid_sources[0x14]	6935	1			T1	11		T3	3		T6	6
valid_sources[0x15]	7805	1			T3	20		T6	22		T7	23
valid_sources[0x16]	6492	1			T1	8		T3	2		T6	24
valid_sources[0x17]	7848	1			T1	5		T3	12		T6	15
valid_sources[0x18]	9553	1			T1	4		T3	6		T6	16
valid_sources[0x19]	25106	1			T1	13		T3	5		T6	12
valid_sources[0x1a]	6959	1			T1	3		T3	6		T6	10
valid_sources[0x1b]	6676	1			T1	13		T3	10		T6	15
valid_sources[0x1c]	7439	1			T1	4		T3	3		T6	19
valid_sources[0x1d]	7645	1			T1	8		T3	6		T6	13
valid_sources[0x1e]	14354	1			T3	18		T6	24		T7	34
valid_sources[0x1f]	6753	1			T1	20		T3	9		T6	22
valid_sources[0x20]	7301	1			T1	1		T3	2		T6	26
valid_sources[0x21]	7906	1			T1	5		T3	5		T6	14
valid_sources[0x22]	7265	1			T1	7		T3	4		T6	21
valid_sources[0x23]	6679	1			T1	6		T3	4		T6	6
valid_sources[0x24]	7897	1			T1	19		T3	7		T6	20
valid_sources[0x25]	20016	1			T1	5		T3	35		T5	45
valid_sources[0x26]	6962	1			T1	22		T3	4		T6	34
valid_sources[0x27]	11282	1			T1	7		T2	1		T3	2
valid_sources[0x28]	6654	1			T1	11		T3	5		T6	37
valid_sources[0x29]	11190	1			T1	1		T3	10		T6	26
valid_sources[0x2a]	6663	1			T1	4		T3	4		T6	12
valid_sources[0x2b]	6379	1			T1	13		T3	4		T6	12
valid_sources[0x2c]	7235	1			T1	13		T3	10		T4	14
valid_sources[0x2d]	11136	1			T1	1		T3	4		T6	20
valid_sources[0x2e]	11056	1			T1	4		T3	3		T6	14
valid_sources[0x2f]	11808	1			T1	2		T3	1		T6	23
valid_sources[0x30]	7250	1			T1	4		T2	8		T3	4
valid_sources[0x31]	6882	1			T1	4		T3	27		T6	9
valid_sources[0x32]	6915	1			T1	5		T2	1		T3	12
valid_sources[0x33]	10641	1			T1	1		T3	2		T6	12
valid_sources[0x34]	8390	1			T1	16		T3	4		T6	11
valid_sources[0x35]	19718	1			T3	3		T6	26		T7	18
valid_sources[0x36]	6880	1			T1	4		T3	10		T6	15
valid_sources[0x37]	7563	1			T1	2		T3	6		T6	8
valid_sources[0x38]	17939	1			T1	1		T3	7		T6	19
valid_sources[0x39]	7659	1			T1	5		T3	1		T6	16
valid_sources[0x3a]	11078	1			T1	7		T2	2		T3	3
valid_sources[0x3b]	6677	1			T1	2		T3	39		T6	24
valid_sources[0x3c]	11424	1			T1	5		T3	3		T6	15
valid_sources[0x3d]	6804	1			T1	10		T3	3		T6	12
valid_sources[0x3e]	6668	1			T1	22		T3	5		T6	16
valid_sources[0x3f]	11602	1			T1	19		T6	16		T7	30
valid_sources[0x40]	6954	1			T1	9		T3	10		T6	22
valid_sources[0x41]	6955	1			T1	10		T3	26		T6	27
valid_sources[0x42]	15667	1			T1	8		T3	7		T6	18
valid_sources[0x43]	7534	1			T1	7		T2	8		T3	20
valid_sources[0x44]	11283	1			T1	9		T3	4		T6	26
valid_sources[0x45]	9929	1			T1	7		T2	2		T3	1
valid_sources[0x46]	19816	1			T1	10		T3	5		T6	13
valid_sources[0x47]	6680	1			T1	3		T3	4		T6	11
valid_sources[0x48]	16044	1			T1	5		T3	3		T6	9
valid_sources[0x49]	11260	1			T1	19		T3	17		T6	11
valid_sources[0x4a]	10915	1			T1	8		T6	20		T7	40
valid_sources[0x4b]	15498	1			T1	2		T3	5		T6	16
valid_sources[0x4c]	20162	1			T1	2		T3	46		T6	18
valid_sources[0x4d]	7586	1			T1	13		T3	1		T5	10
valid_sources[0x4e]	15566	1			T1	6		T3	2		T6	12
valid_sources[0x4f]	7003	1			T1	11		T3	3		T6	12
valid_sources[0x50]	7080	1			T1	11		T3	8		T6	18
valid_sources[0x51]	11788	1			T1	5		T2	1		T3	8
valid_sources[0x52]	8765	1			T1	11		T3	3		T6	33
valid_sources[0x53]	8651	1			T1	9		T3	23		T6	5
valid_sources[0x54]	6623	1			T1	2		T3	46		T6	17
valid_sources[0x55]	7209	1			T1	1		T3	10		T6	25
valid_sources[0x56]	9312	1			T1	10		T3	6		T6	17
valid_sources[0x57]	7716	1			T1	16		T3	9		T6	13
valid_sources[0x58]	6726	1			T1	9		T3	16		T6	24
valid_sources[0x59]	7685	1			T1	5		T3	6		T6	6
valid_sources[0x5a]	8566	1			T1	9		T3	1		T6	18
valid_sources[0x5b]	6705	1			T1	10		T3	3		T6	10
valid_sources[0x5c]	7011	1			T1	5		T3	5		T5	16
valid_sources[0x5d]	7846	1			T1	13		T3	3		T6	18
valid_sources[0x5e]	6675	1			T1	3		T3	33		T6	9
valid_sources[0x5f]	6878	1			T2	2		T3	3		T6	28
valid_sources[0x60]	6725	1			T1	27		T3	4		T6	14
valid_sources[0x61]	16641	1			T1	20		T2	3		T3	2
valid_sources[0x62]	7753	1			T1	926		T3	9		T6	26
valid_sources[0x63]	7851	1			T1	12		T3	8		T6	24
valid_sources[0x64]	7195	1			T1	14		T3	3		T6	12
valid_sources[0x65]	7975	1			T1	7		T3	31		T6	30
valid_sources[0x66]	7033	1			T1	9		T3	8		T6	28
valid_sources[0x67]	22053	1			T1	1		T3	3		T6	10
valid_sources[0x68]	7509	1			T1	2		T3	6		T6	16
valid_sources[0x69]	6313	1			T1	15		T3	8		T6	14
valid_sources[0x6a]	6927	1			T1	1		T3	10		T6	17
valid_sources[0x6b]	8784	1			T1	18		T3	15		T6	26
valid_sources[0x6c]	9570	1			T1	5		T3	2		T6	12
valid_sources[0x6d]	6832	1			T1	4		T3	3		T6	15
valid_sources[0x6e]	9528	1			T1	7		T3	7		T6	24
valid_sources[0x6f]	6531	1			T1	4		T3	9		T6	29
valid_sources[0x70]	11341	1			T1	3		T3	7		T6	18
valid_sources[0x71]	8526	1			T1	17		T3	1		T6	10
valid_sources[0x72]	6902	1			T1	3		T3	3		T6	19
valid_sources[0x73]	9076	1			T1	5		T2	2		T3	12
valid_sources[0x74]	8419	1			T1	1		T3	1		T6	52
valid_sources[0x75]	7350	1			T1	2		T3	2		T6	10
valid_sources[0x76]	8038	1			T1	5		T3	5		T6	13
valid_sources[0x77]	6614	1			T1	3		T3	4		T6	28
valid_sources[0x78]	9646	1			T1	11		T3	1		T4	130
valid_sources[0x79]	6855	1			T1	5		T3	3		T6	20
valid_sources[0x7a]	7984	1			T1	3		T3	9		T6	25
valid_sources[0x7b]	13830	1			T1	17		T3	4		T6	8
valid_sources[0x7c]	6786	1			T1	6		T2	5		T3	5
valid_sources[0x7d]	7084	1			T1	12		T3	2		T5	10
valid_sources[0x7e]	13197	1			T1	4		T3	5		T6	18
valid_sources[0x7f]	9587	1			T1	2		T3	36		T6	13
valid_sources[0x80]	16242	1			T1	6		T3	12		T6	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1026523

1

T1

1262

T3

848

T4

42

values[0x0]

all_enables

biggest_size

79841

1

T1

89

T2

10

T3

67

values[0x1]

all_enables

biggest_size

58376

1

T1

67

T2

25

T3

39