Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29378	1			T1	30		T3	9		T6	202
auto[PWRUP]	116	1			T6	1		T42	2		T16	1
auto[ONEST_0]	72	1			T42	1		T52	1		T49	2
auto[ONEST_021]	18	1			T6	1		T27	1		T52	1
auto[ONEST_1]	84	1			T6	2		T51	1		T52	1
auto[ONEST_DONE]	7	1			T51	1		T49	2		T265	1
auto[LP_0]	121	1			T6	2		T42	1		T51	1
auto[LP_021]	31	1			T42	1		T51	1		T52	3
auto[LP_1]	143	1			T6	3		T42	3		T16	1
auto[LP_EVAL]	62	1			T51	1		T49	4		T43	7
auto[LP_SLP]	469	1			T6	5		T42	5		T51	3
auto[LP_PWRUP]	38	1			T51	1		T27	1		T52	1
auto[NP_0]	163	1			T6	3		T42	2		T51	2
auto[NP_021]	29	1			T42	2		T49	2		T50	1
auto[NP_1]	158	1			T6	1		T51	1		T27	3
auto[NP_EVAL]	38	1			T6	1		T42	1		T16	1
auto[NP_DONE]	2	1			T349	1		T350	1		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T47

1

T351

1

T37

1

min

28849

1

T1

30

T3

9

T6

198

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28856	1			T1	30		T3	9		T6	198
pow[0x1]	10	1			T352	1		T353	1		T354	1
pow[0x2]	19	1			T52	2		T355	1		T105	1
pow[0x3]	30	1			T6	1		T51	1		T52	1
pow[0x4]	71	1			T6	1		T42	2		T51	1
pow[0x5]	133	1			T6	1		T42	1		T51	3
pow[0x6]	247	1			T6	5		T42	3		T51	4
pow[0x7]	527	1			T6	5		T42	11		T51	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

198

1

T6

1

T42

2

T51

3

min

28393

1

T1

30

T3

9

T6

194

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28393	1			T1	30		T3	9		T6	194
pow[0x2]	1	1			T356	1		-	-		-	-
pow[0x5]	1	1			T46	1		-	-		-	-
pow[0x6]	1	1			T357	1		-	-		-	-
pow[0x7]	2	1			T38	1		T358	1		-	-
pow[0x8]	5	1			T359	1		T65	1		T360	1
pow[0x9]	8	1			T105	1		T265	1		T65	1
pow[0xa]	16	1			T16	1		T52	1		T121	1
pow[0xb]	38	1			T6	1		T42	1		T49	2
pow[0xc]	65	1			T42	3		T16	1		T52	1
pow[0xd]	142	1			T42	5		T27	2		T52	1
pow[0xe]	281	1			T6	4		T42	2		T51	5
pow[0xf]	590	1			T6	6		T42	4		T51	4