Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2265	1			T6	23		T7	2		T42	19
auto[PWRUP]	137	1			T6	3		T42	3		T51	1
auto[ONEST_0]	74	1			T42	1		T51	1		T52	2
auto[ONEST_021]	18	1			T6	1		T27	1		T37	1
auto[ONEST_1]	88	1			T51	3		T16	1		T52	1
auto[ONEST_DONE]	3	1			T105	1		T18	1		T349	1
auto[LP_0]	116	1			T6	3		T42	1		T27	2
auto[LP_021]	26	1			T50	1		T105	1		T54	1
auto[LP_1]	131	1			T42	2		T51	1		T52	5
auto[LP_EVAL]	64	1			T6	2		T16	1		T52	2
auto[LP_SLP]	551	1			T6	3		T42	10		T51	7
auto[LP_PWRUP]	25	1			T42	1		T51	1		T50	1
auto[NP_0]	205	1			T6	2		T42	2		T51	5
auto[NP_021]	57	1			T6	1		T42	1		T51	2
auto[NP_1]	221	1			T6	1		T51	3		T16	3
auto[NP_EVAL]	33	1			T6	1		T50	1		T43	1
auto[NP_DONE]	1	1			T361	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T49

1

T105

1

T362

1

min

1979

1

T6

10

T7

2

T42

12

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1987	1			T6	10		T7	2		T42	12
pow[0x1]	8	1			T51	1		T49	2		T17	1
pow[0x2]	13	1			T49	1		T54	1		T363	2
pow[0x3]	30	1			T6	1		T51	1		T49	2
pow[0x4]	69	1			T6	1		T42	1		T49	1
pow[0x5]	129	1			T6	3		T42	3		T51	2
pow[0x6]	270	1			T6	6		T42	6		T51	5
pow[0x7]	494	1			T6	2		T42	4		T51	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

200

1

T6

2

T42

1

T51

4

min

1379

1

T6

8

T7

2

T42

1

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1387	1			T6	8		T7	2		T42	1
pow[0x1]	10	1			T41	1		T17	1		T364	4
pow[0x2]	27	1			T16	1		T17	1		T18	5
pow[0x3]	40	1			T40	5		T43	2		T45	3
pow[0x4]	43	1			T16	3		T43	1		T47	2
pow[0x5]	3	1			T49	1		T43	1		T351	1
pow[0x7]	4	1			T49	1		T365	1		T366	1
pow[0x8]	7	1			T42	1		T55	1		T359	1
pow[0x9]	14	1			T51	1		T16	1		T27	1
pow[0xa]	16	1			T6	1		T49	1		T367	1
pow[0xb]	43	1			T42	1		T27	1		T49	2
pow[0xc]	65	1			T42	1		T51	2		T16	2
pow[0xd]	117	1			T6	1		T51	2		T16	1
pow[0xe]	326	1			T6	5		T42	4		T51	4
pow[0xf]	565	1			T6	9		T42	10		T51	8