Assert Coverage for Module :
adc_ctrl_fsm_sva
Assertion Details
FsmDebugOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31670177 |
31589198 |
0 |
0 |
T1 |
107916 |
107852 |
0 |
0 |
T2 |
1155 |
1063 |
0 |
0 |
T3 |
68686 |
68601 |
0 |
0 |
T4 |
1153 |
1077 |
0 |
0 |
T5 |
1145 |
1065 |
0 |
0 |
T6 |
34433 |
34022 |
0 |
0 |
T7 |
66776 |
66581 |
0 |
0 |
T8 |
97159 |
97091 |
0 |
0 |
T9 |
1164 |
1088 |
0 |
0 |
T10 |
9043 |
8970 |
0 |
0 |
FsmStateHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1164 |
1164 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
6 |
6 |
0 |
0 |
T7 |
3 |
3 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
FsmStateSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31670177 |
6587 |
0 |
0 |
T1 |
107916 |
30 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
9 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
34433 |
8 |
0 |
0 |
T7 |
66776 |
18 |
0 |
0 |
T8 |
97159 |
20 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T15 |
0 |
15 |
0 |
0 |
LpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1164 |
1164 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
6 |
6 |
0 |
0 |
T7 |
3 |
3 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
LpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31670177 |
6587 |
0 |
0 |
T1 |
107916 |
30 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
9 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
34433 |
8 |
0 |
0 |
T7 |
66776 |
18 |
0 |
0 |
T8 |
97159 |
20 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T15 |
0 |
15 |
0 |
0 |
NpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1164 |
1164 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
6 |
6 |
0 |
0 |
T7 |
3 |
3 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31670177 |
6587 |
0 |
0 |
T1 |
107916 |
30 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
9 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
34433 |
8 |
0 |
0 |
T7 |
66776 |
18 |
0 |
0 |
T8 |
97159 |
20 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T15 |
0 |
15 |
0 |
0 |
PwrupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1164 |
1164 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
6 |
6 |
0 |
0 |
T7 |
3 |
3 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
PwrupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31670177 |
6587 |
0 |
0 |
T1 |
107916 |
30 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
9 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
34433 |
8 |
0 |
0 |
T7 |
66776 |
18 |
0 |
0 |
T8 |
97159 |
20 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T15 |
0 |
15 |
0 |
0 |
WakeupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1164 |
1164 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
6 |
6 |
0 |
0 |
T7 |
3 |
3 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
WakeupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31670177 |
6587 |
0 |
0 |
T1 |
107916 |
30 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
9 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
34433 |
8 |
0 |
0 |
T7 |
66776 |
18 |
0 |
0 |
T8 |
97159 |
20 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T15 |
0 |
15 |
0 |
0 |