Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
345843 |
0 |
0 |
T1 |
11363886 |
126 |
0 |
0 |
T2 |
8146957 |
93 |
0 |
0 |
T3 |
7761708 |
84 |
0 |
0 |
T4 |
5284058 |
102 |
0 |
0 |
T5 |
5575811 |
102 |
0 |
0 |
T6 |
8985578 |
1163 |
0 |
0 |
T7 |
18863912 |
84 |
0 |
0 |
T8 |
6271717 |
126 |
0 |
0 |
T9 |
2898996 |
102 |
0 |
0 |
T10 |
8325858 |
82 |
0 |
0 |
T11 |
0 |
36 |
0 |
0 |
T12 |
0 |
36 |
0 |
0 |
T13 |
0 |
72 |
0 |
0 |
T14 |
0 |
36 |
0 |
0 |
T15 |
0 |
56 |
0 |
0 |
T16 |
19045 |
1 |
0 |
0 |
T26 |
973 |
0 |
0 |
0 |
T27 |
17856 |
0 |
0 |
0 |
T28 |
73573 |
0 |
0 |
0 |
T29 |
88 |
0 |
0 |
0 |
T30 |
97592 |
0 |
0 |
0 |
T31 |
33840 |
0 |
0 |
0 |
T32 |
39497 |
0 |
0 |
0 |
T33 |
32073 |
0 |
0 |
0 |
T34 |
72046 |
0 |
0 |
0 |
T42 |
0 |
433 |
0 |
0 |
T56 |
204327 |
9 |
0 |
0 |
T84 |
0 |
20 |
0 |
0 |
T129 |
0 |
3 |
0 |
0 |
T153 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
348311 |
0 |
0 |
T1 |
11363886 |
126 |
0 |
0 |
T2 |
7720419 |
93 |
0 |
0 |
T3 |
7486954 |
84 |
0 |
0 |
T4 |
5008195 |
102 |
0 |
0 |
T5 |
5284577 |
102 |
0 |
0 |
T6 |
8615581 |
1163 |
0 |
0 |
T7 |
18001112 |
84 |
0 |
0 |
T8 |
6130831 |
126 |
0 |
0 |
T9 |
2748684 |
102 |
0 |
0 |
T10 |
7905265 |
82 |
0 |
0 |
T11 |
0 |
36 |
0 |
0 |
T12 |
0 |
36 |
0 |
0 |
T13 |
0 |
72 |
0 |
0 |
T14 |
0 |
36 |
0 |
0 |
T15 |
0 |
56 |
0 |
0 |
T16 |
485684 |
10 |
0 |
0 |
T26 |
482192 |
0 |
0 |
0 |
T27 |
133934 |
0 |
0 |
0 |
T28 |
367872 |
0 |
0 |
0 |
T29 |
7185 |
0 |
0 |
0 |
T30 |
233418 |
0 |
0 |
0 |
T31 |
372243 |
0 |
0 |
0 |
T32 |
197493 |
0 |
0 |
0 |
T33 |
400932 |
0 |
0 |
0 |
T34 |
162369 |
0 |
0 |
0 |
T42 |
0 |
433 |
0 |
0 |
T56 |
833 |
9 |
0 |
0 |
T84 |
0 |
20 |
0 |
0 |
T129 |
0 |
3 |
0 |
0 |
T153 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 5 | 2 | 40.00 |
Logical | 5 | 2 | 40.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 5 | 2 | 40.00 |
Logical | 5 | 2 | 40.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 6 | 75.00 |
Logical | 8 | 6 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T16,T40,T41 |
1 | 0 | Covered | T16,T40,T41 |
1 | 1 | Not Covered | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T16,T40,T41 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T16,T40,T41 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
79 |
0 |
0 |
T16 |
19045 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T26 |
973 |
0 |
0 |
0 |
T27 |
17856 |
0 |
0 |
0 |
T28 |
73573 |
0 |
0 |
0 |
T29 |
88 |
0 |
0 |
0 |
T30 |
97592 |
0 |
0 |
0 |
T31 |
33840 |
0 |
0 |
0 |
T32 |
39497 |
0 |
0 |
0 |
T33 |
32073 |
0 |
0 |
0 |
T34 |
72046 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T44 |
0 |
1 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
377 |
0 |
0 |
T16 |
485684 |
10 |
0 |
0 |
T17 |
0 |
8 |
0 |
0 |
T18 |
0 |
9 |
0 |
0 |
T26 |
482192 |
0 |
0 |
0 |
T27 |
133934 |
0 |
0 |
0 |
T28 |
367872 |
0 |
0 |
0 |
T29 |
7185 |
0 |
0 |
0 |
T30 |
233418 |
0 |
0 |
0 |
T31 |
372243 |
0 |
0 |
0 |
T32 |
197493 |
0 |
0 |
0 |
T33 |
400932 |
0 |
0 |
0 |
T34 |
162369 |
0 |
0 |
0 |
T40 |
0 |
10 |
0 |
0 |
T41 |
0 |
5 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T44 |
0 |
4 |
0 |
0 |
T45 |
0 |
5 |
0 |
0 |
T46 |
0 |
5 |
0 |
0 |
T47 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
38206 |
0 |
0 |
T1 |
107916 |
9 |
0 |
0 |
T2 |
1155 |
41 |
0 |
0 |
T3 |
68686 |
6 |
0 |
0 |
T4 |
1153 |
41 |
0 |
0 |
T5 |
1145 |
41 |
0 |
0 |
T6 |
52855 |
327 |
0 |
0 |
T7 |
66776 |
6 |
0 |
0 |
T8 |
97159 |
9 |
0 |
0 |
T9 |
1164 |
41 |
0 |
0 |
T10 |
9043 |
41 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
38359 |
0 |
0 |
T1 |
523411 |
9 |
0 |
0 |
T2 |
427693 |
41 |
0 |
0 |
T3 |
343440 |
6 |
0 |
0 |
T4 |
277016 |
41 |
0 |
0 |
T5 |
292379 |
41 |
0 |
0 |
T6 |
422852 |
327 |
0 |
0 |
T7 |
929576 |
6 |
0 |
0 |
T8 |
238045 |
9 |
0 |
0 |
T9 |
151476 |
41 |
0 |
0 |
T10 |
429636 |
41 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
38295 |
0 |
0 |
T1 |
523411 |
9 |
0 |
0 |
T2 |
427693 |
41 |
0 |
0 |
T3 |
343440 |
6 |
0 |
0 |
T4 |
277016 |
41 |
0 |
0 |
T5 |
292379 |
41 |
0 |
0 |
T6 |
422852 |
327 |
0 |
0 |
T7 |
929576 |
6 |
0 |
0 |
T8 |
238045 |
9 |
0 |
0 |
T9 |
151476 |
41 |
0 |
0 |
T10 |
429636 |
41 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
38309 |
0 |
0 |
T1 |
107916 |
9 |
0 |
0 |
T2 |
1155 |
41 |
0 |
0 |
T3 |
68686 |
6 |
0 |
0 |
T4 |
1153 |
41 |
0 |
0 |
T5 |
1145 |
41 |
0 |
0 |
T6 |
52855 |
327 |
0 |
0 |
T7 |
66776 |
6 |
0 |
0 |
T8 |
97159 |
9 |
0 |
0 |
T9 |
1164 |
41 |
0 |
0 |
T10 |
9043 |
41 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
17837 |
0 |
0 |
T1 |
107916 |
6 |
0 |
0 |
T2 |
1155 |
20 |
0 |
0 |
T3 |
68686 |
4 |
0 |
0 |
T4 |
1153 |
1 |
0 |
0 |
T5 |
1145 |
1 |
0 |
0 |
T6 |
52855 |
163 |
0 |
0 |
T7 |
66776 |
4 |
0 |
0 |
T8 |
97159 |
6 |
0 |
0 |
T9 |
1164 |
1 |
0 |
0 |
T10 |
9043 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
17927 |
0 |
0 |
T1 |
523411 |
6 |
0 |
0 |
T2 |
427693 |
20 |
0 |
0 |
T3 |
343440 |
4 |
0 |
0 |
T4 |
277016 |
1 |
0 |
0 |
T5 |
292379 |
1 |
0 |
0 |
T6 |
422852 |
163 |
0 |
0 |
T7 |
929576 |
4 |
0 |
0 |
T8 |
238045 |
6 |
0 |
0 |
T9 |
151476 |
1 |
0 |
0 |
T10 |
429636 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
17914 |
0 |
0 |
T1 |
523411 |
6 |
0 |
0 |
T2 |
427693 |
20 |
0 |
0 |
T3 |
343440 |
4 |
0 |
0 |
T4 |
277016 |
1 |
0 |
0 |
T5 |
292379 |
1 |
0 |
0 |
T6 |
422852 |
163 |
0 |
0 |
T7 |
929576 |
4 |
0 |
0 |
T8 |
238045 |
6 |
0 |
0 |
T9 |
151476 |
1 |
0 |
0 |
T10 |
429636 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
17914 |
0 |
0 |
T1 |
107916 |
6 |
0 |
0 |
T2 |
1155 |
20 |
0 |
0 |
T3 |
68686 |
4 |
0 |
0 |
T4 |
1153 |
1 |
0 |
0 |
T5 |
1145 |
1 |
0 |
0 |
T6 |
52855 |
163 |
0 |
0 |
T7 |
66776 |
4 |
0 |
0 |
T8 |
97159 |
6 |
0 |
0 |
T9 |
1164 |
1 |
0 |
0 |
T10 |
9043 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
13895 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
153 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
127 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14035 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
153 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
127 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
13995 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
153 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
127 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
13995 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
153 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
127 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
13929 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
153 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
127 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14063 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
153 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
127 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14024 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
153 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
127 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
14024 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
153 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
127 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
19669 |
0 |
0 |
T1 |
107916 |
6 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
4 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
209 |
0 |
0 |
T7 |
66776 |
4 |
0 |
0 |
T8 |
97159 |
6 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
0 |
4 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T42 |
0 |
193 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
19762 |
0 |
0 |
T1 |
523411 |
6 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
4 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
209 |
0 |
0 |
T7 |
929576 |
4 |
0 |
0 |
T8 |
238045 |
6 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
0 |
4 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T42 |
0 |
193 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
19751 |
0 |
0 |
T1 |
523411 |
6 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
4 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
209 |
0 |
0 |
T7 |
929576 |
4 |
0 |
0 |
T8 |
238045 |
6 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
0 |
4 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T42 |
0 |
193 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
19751 |
0 |
0 |
T1 |
107916 |
6 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
4 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
209 |
0 |
0 |
T7 |
66776 |
4 |
0 |
0 |
T8 |
97159 |
6 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
0 |
4 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T42 |
0 |
193 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
2000 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
2 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2086 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
2 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2075 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
2 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
2075 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
2 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1899 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1984 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1975 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1975 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1856 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1941 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1929 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1929 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1875 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1964 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1953 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1953 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1886 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1971 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1960 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1960 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1852 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1936 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1925 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1925 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1870 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1958 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1946 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1946 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1849 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1936 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1925 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1925 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
2009 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
2 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2096 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
2 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2084 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
2 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
2084 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
2 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1897 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1981 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1971 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1971 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1883 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1972 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1961 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1961 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1891 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1980 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1969 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1969 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1892 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1980 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1969 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1969 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1880 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1964 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1953 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1953 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1878 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1960 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1951 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1951 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1907 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1988 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1977 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
3 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1977 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
3 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T15 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T15 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1350 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
0 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1436 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
0 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T15 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T15 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1426 |
0 |
0 |
T1 |
523411 |
3 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
2 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
1 |
0 |
0 |
T7 |
929576 |
2 |
0 |
0 |
T8 |
238045 |
0 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
1426 |
0 |
0 |
T1 |
107916 |
3 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
2 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
1 |
0 |
0 |
T7 |
66776 |
2 |
0 |
0 |
T8 |
97159 |
0 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34291039 |
67137 |
0 |
0 |
T1 |
107916 |
237 |
0 |
0 |
T2 |
1155 |
0 |
0 |
0 |
T3 |
68686 |
165 |
0 |
0 |
T4 |
1153 |
0 |
0 |
0 |
T5 |
1145 |
0 |
0 |
0 |
T6 |
52855 |
98 |
0 |
0 |
T7 |
66776 |
158 |
0 |
0 |
T8 |
97159 |
236 |
0 |
0 |
T9 |
1164 |
0 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T11 |
0 |
77 |
0 |
0 |
T12 |
0 |
77 |
0 |
0 |
T13 |
0 |
144 |
0 |
0 |
T14 |
0 |
89 |
0 |
0 |
T15 |
0 |
141 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
67223 |
0 |
0 |
T1 |
523411 |
237 |
0 |
0 |
T2 |
427693 |
0 |
0 |
0 |
T3 |
343440 |
165 |
0 |
0 |
T4 |
277016 |
0 |
0 |
0 |
T5 |
292379 |
0 |
0 |
0 |
T6 |
422852 |
98 |
0 |
0 |
T7 |
929576 |
158 |
0 |
0 |
T8 |
238045 |
236 |
0 |
0 |
T9 |
151476 |
0 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T11 |
0 |
77 |
0 |
0 |
T12 |
0 |
77 |
0 |
0 |
T13 |
0 |
144 |
0 |
0 |
T14 |
0 |
89 |
0 |
0 |
T15 |
0 |
141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T5 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T2,T4,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T4,T5 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T2,T4,T5 |
Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
6489 |
0 |
0 |
T2 |
427693 |
11 |
0 |
0 |
T3 |
343440 |
0 |
0 |
0 |
T4 |
277016 |
20 |
0 |
0 |
T5 |
292379 |
20 |
0 |
0 |
T6 |
422852 |
55 |
0 |
0 |
T7 |
929576 |
0 |
0 |
0 |
T8 |
238045 |
0 |
0 |
0 |
T9 |
151476 |
20 |
0 |
0 |
T10 |
429636 |
0 |
0 |
0 |
T42 |
0 |
43 |
0 |
0 |
T56 |
204327 |
9 |
0 |
0 |
T84 |
0 |
20 |
0 |
0 |
T129 |
0 |
3 |
0 |
0 |
T153 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34206321 |
6490 |
0 |
0 |
T2 |
1155 |
11 |
0 |
0 |
T3 |
68686 |
0 |
0 |
0 |
T4 |
1153 |
20 |
0 |
0 |
T5 |
1145 |
20 |
0 |
0 |
T6 |
52855 |
55 |
0 |
0 |
T7 |
66776 |
0 |
0 |
0 |
T8 |
97159 |
0 |
0 |
0 |
T9 |
1164 |
20 |
0 |
0 |
T10 |
9043 |
0 |
0 |
0 |
T42 |
0 |
43 |
0 |
0 |
T56 |
833 |
9 |
0 |
0 |
T84 |
0 |
20 |
0 |
0 |
T129 |
0 |
3 |
0 |
0 |
T153 |
0 |
20 |
0 |
0 |