Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2569	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2633	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2491	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2631	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2479	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2384	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2887	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2448	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2663	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2708	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2666	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2484	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2501	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2694	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2541	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2382	0	0
adc_en_ctl_rd_A	2147483647	1948	0	0
adc_fsm_rst_rd_A	2147483647	1685	0	0
adc_intr_ctl_rd_A	2147483647	2439	0	0
adc_lp_sample_ctl_rd_A	2147483647	1588	0	0
adc_pd_ctl_rd_A	2147483647	2253	0	0
adc_sample_ctl_rd_A	2147483647	1569	0	0
adc_wakeup_ctl_rd_A	2147483647	1989	0	0
intr_enable_rd_A	2147483647	2226	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2569	0	0
T16	485684	43	0	0
T17	0	17	0	0
T18	0	33	0	0
T19	0	12	0	0
T20	0	25	0	0
T21	0	20	0	0
T22	0	2	0	0
T23	0	27	0	0
T24	0	22	0	0
T25	0	36	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2633	0	0
T16	485684	30	0	0
T17	0	22	0	0
T18	0	28	0	0
T19	0	22	0	0
T20	0	27	0	0
T21	0	28	0	0
T22	0	11	0	0
T23	0	7	0	0
T24	0	30	0	0
T25	0	29	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2491	0	0
T16	485684	36	0	0
T17	0	32	0	0
T18	0	20	0	0
T19	0	11	0	0
T20	0	21	0	0
T21	0	29	0	0
T22	0	11	0	0
T23	0	13	0	0
T24	0	24	0	0
T25	0	13	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2631	0	0
T16	485684	31	0	0
T17	0	16	0	0
T18	0	16	0	0
T19	0	39	0	0
T20	0	11	0	0
T21	0	22	0	0
T22	0	2	0	0
T23	0	29	0	0
T24	0	12	0	0
T25	0	50	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2479	0	0
T16	485684	40	0	0
T17	0	13	0	0
T18	0	35	0	0
T19	0	22	0	0
T20	0	25	0	0
T21	0	18	0	0
T22	0	15	0	0
T23	0	23	0	0
T24	0	16	0	0
T25	0	22	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2384	0	0
T16	485684	36	0	0
T17	0	20	0	0
T18	0	28	0	0
T19	0	22	0	0
T20	0	25	0	0
T21	0	33	0	0
T22	0	7	0	0
T23	0	28	0	0
T24	0	14	0	0
T25	0	40	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2887	0	0
T16	485684	21	0	0
T17	0	28	0	0
T18	0	41	0	0
T19	0	33	0	0
T20	0	37	0	0
T21	0	35	0	0
T22	0	15	0	0
T23	0	24	0	0
T24	0	33	0	0
T25	0	29	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2448	0	0
T16	485684	37	0	0
T17	0	16	0	0
T18	0	35	0	0
T19	0	14	0	0
T20	0	26	0	0
T21	0	32	0	0
T22	0	20	0	0
T23	0	17	0	0
T24	0	28	0	0
T25	0	23	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2663	0	0
T16	485684	47	0	0
T17	0	31	0	0
T18	0	41	0	0
T19	0	26	0	0
T20	0	39	0	0
T21	0	53	0	0
T23	0	20	0	0
T24	0	40	0	0
T25	0	24	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0
T35	0	23	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2708	0	0
T16	485684	51	0	0
T17	0	23	0	0
T18	0	24	0	0
T19	0	20	0	0
T20	0	22	0	0
T21	0	22	0	0
T22	0	4	0	0
T23	0	14	0	0
T24	0	19	0	0
T25	0	38	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2666	0	0
T16	485684	29	0	0
T17	0	26	0	0
T18	0	24	0	0
T19	0	22	0	0
T20	0	33	0	0
T21	0	29	0	0
T22	0	4	0	0
T23	0	22	0	0
T24	0	26	0	0
T25	0	38	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2484	0	0
T16	485684	33	0	0
T17	0	9	0	0
T18	0	44	0	0
T19	0	40	0	0
T20	0	20	0	0
T21	0	26	0	0
T22	0	12	0	0
T23	0	21	0	0
T24	0	18	0	0
T25	0	32	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2501	0	0
T16	485684	42	0	0
T17	0	25	0	0
T18	0	34	0	0
T19	0	27	0	0
T20	0	23	0	0
T21	0	41	0	0
T22	0	4	0	0
T23	0	15	0	0
T24	0	27	0	0
T25	0	28	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2694	0	0
T16	485684	34	0	0
T17	0	12	0	0
T18	0	22	0	0
T19	0	16	0	0
T20	0	32	0	0
T21	0	37	0	0
T22	0	7	0	0
T23	0	11	0	0
T24	0	33	0	0
T25	0	35	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2541	0	0
T16	485684	50	0	0
T17	0	31	0	0
T18	0	24	0	0
T19	0	18	0	0
T20	0	29	0	0
T21	0	39	0	0
T22	0	9	0	0
T23	0	16	0	0
T24	0	19	0	0
T25	0	28	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2382	0	0
T16	485684	36	0	0
T17	0	21	0	0
T18	0	38	0	0
T19	0	23	0	0
T20	0	38	0	0
T21	0	39	0	0
T22	0	8	0	0
T23	0	15	0	0
T24	0	31	0	0
T25	0	36	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1948	0	0
T16	485684	23	0	0
T17	0	19	0	0
T18	0	20	0	0
T19	0	23	0	0
T20	0	29	0	0
T21	0	32	0	0
T22	0	14	0	0
T23	0	28	0	0
T24	0	24	0	0
T25	0	29	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1685	0	0
T16	485684	41	0	0
T17	0	28	0	0
T18	0	42	0	0
T19	0	28	0	0
T20	0	37	0	0
T21	0	18	0	0
T22	0	13	0	0
T23	0	9	0	0
T24	0	33	0	0
T25	0	28	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2439	0	0
T16	485684	34	0	0
T17	0	22	0	0
T18	0	42	0	0
T19	0	24	0	0
T20	0	36	0	0
T21	0	21	0	0
T22	0	3	0	0
T23	0	15	0	0
T24	0	28	0	0
T25	0	25	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1588	0	0
T16	485684	31	0	0
T17	0	27	0	0
T18	0	26	0	0
T19	0	25	0	0
T20	0	29	0	0
T21	0	37	0	0
T22	0	9	0	0
T23	0	26	0	0
T24	0	16	0	0
T25	0	51	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2253	0	0
T16	485684	45	0	0
T17	0	13	0	0
T18	0	37	0	0
T19	0	21	0	0
T20	0	25	0	0
T21	0	35	0	0
T22	0	6	0	0
T23	0	21	0	0
T24	0	30	0	0
T25	0	26	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1569	0	0
T16	485684	35	0	0
T17	0	21	0	0
T18	0	24	0	0
T19	0	16	0	0
T20	0	34	0	0
T21	0	33	0	0
T22	0	11	0	0
T23	0	16	0	0
T24	0	20	0	0
T25	0	28	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1989	0	0
T16	485684	36	0	0
T17	0	36	0	0
T18	0	16	0	0
T19	0	13	0	0
T20	0	26	0	0
T21	0	30	0	0
T22	0	18	0	0
T23	0	23	0	0
T24	0	27	0	0
T25	0	29	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	0	0	0
T29	7185	0	0	0
T30	233418	0	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2226	0	0
T16	485684	45	0	0
T17	0	25	0	0
T18	0	20	0	0
T19	0	42	0	0
T26	482192	0	0	0
T27	133934	0	0	0
T28	367872	26	0	0
T29	7185	0	0	0
T30	233418	7	0	0
T31	372243	0	0	0
T32	197493	0	0	0
T33	400932	0	0	0
T34	162369	0	0	0
T36	0	4	0	0
T37	0	29	0	0
T38	0	23	0	0
T39	0	28	0	0