Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1249498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1217938

1

T1

1357

T2

6356

T3

1437

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2171306	1			T1	2482		T2	11993		T3	2506
values[0x0]	147486	1			T1	141		T2	377		T3	142
values[0x1]	148644	1			T1	152		T2	406		T3	156

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1001099	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1466337

1

T1

1626

T2

7635

T3

1717

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8198	1			T1	19		T2	35		T3	11
valid_sources[0x01]	7722	1			T1	5		T2	38		T3	15
valid_sources[0x02]	10611	1			T1	8		T2	37		T3	19
valid_sources[0x03]	7166	1			T1	13		T2	50		T3	13
valid_sources[0x04]	14329	1			T1	11		T2	29		T3	5
valid_sources[0x05]	6539	1			T1	28		T2	31		T3	5
valid_sources[0x06]	12156	1			T1	13		T2	25		T3	9
valid_sources[0x07]	7515	1			T1	13		T2	19		T3	3
valid_sources[0x08]	11537	1			T1	8		T2	48		T3	11
valid_sources[0x09]	12538	1			T1	3		T2	37		T3	13
valid_sources[0x0a]	8187	1			T1	13		T2	28		T3	10
valid_sources[0x0b]	10697	1			T1	10		T2	25		T3	4
valid_sources[0x0c]	7196	1			T1	4		T2	13		T3	4
valid_sources[0x0d]	7362	1			T1	8		T2	33		T3	4
valid_sources[0x0e]	11524	1			T1	9		T2	38		T3	9
valid_sources[0x0f]	8036	1			T1	8		T2	23		T3	16
valid_sources[0x10]	8070	1			T1	15		T2	20		T3	18
valid_sources[0x11]	7078	1			T1	23		T2	45		T3	15
valid_sources[0x12]	21416	1			T1	10		T2	34		T3	16
valid_sources[0x13]	7846	1			T1	7		T2	33		T3	8
valid_sources[0x14]	15563	1			T1	12		T2	42		T3	1
valid_sources[0x15]	7020	1			T1	6		T2	25		T3	10
valid_sources[0x16]	8377	1			T1	11		T2	26		T3	18
valid_sources[0x17]	13705	1			T1	12		T2	19		T3	1
valid_sources[0x18]	16508	1			T1	6		T2	61		T3	10
valid_sources[0x19]	11560	1			T1	15		T2	33		T3	21
valid_sources[0x1a]	8781	1			T1	7		T2	16		T3	11
valid_sources[0x1b]	7578	1			T1	14		T2	46		T3	6
valid_sources[0x1c]	7124	1			T1	14		T2	30		T3	14
valid_sources[0x1d]	6821	1			T1	13		T2	24		T3	6
valid_sources[0x1e]	7740	1			T1	6		T2	34		T3	11
valid_sources[0x1f]	10077	1			T1	24		T2	26		T3	13
valid_sources[0x20]	8248	1			T1	13		T2	32		T3	20
valid_sources[0x21]	12370	1			T1	7		T2	14		T3	12
valid_sources[0x22]	11747	1			T1	12		T2	16		T3	13
valid_sources[0x23]	24280	1			T1	14		T2	25		T3	9
valid_sources[0x24]	7014	1			T1	8		T2	71		T3	9
valid_sources[0x25]	7080	1			T1	7		T2	32		T3	20
valid_sources[0x26]	13968	1			T1	3		T2	86		T3	10
valid_sources[0x27]	13040	1			T1	5		T2	43		T3	7
valid_sources[0x28]	6845	1			T1	23		T2	51		T3	2
valid_sources[0x29]	7487	1			T1	11		T2	33		T3	8
valid_sources[0x2a]	7883	1			T1	17		T2	51		T3	32
valid_sources[0x2b]	11631	1			T1	24		T2	27		T3	5
valid_sources[0x2c]	9225	1			T1	6		T2	16		T3	10
valid_sources[0x2d]	6788	1			T1	15		T2	66		T3	7
valid_sources[0x2e]	8029	1			T1	10		T2	37		T3	16
valid_sources[0x2f]	7643	1			T1	22		T2	28		T3	10
valid_sources[0x30]	7116	1			T1	5		T2	55		T3	9
valid_sources[0x31]	7274	1			T1	18		T2	19		T3	10
valid_sources[0x32]	7591	1			T1	15		T2	45		T3	11
valid_sources[0x33]	7117	1			T1	12		T2	32		T3	10
valid_sources[0x34]	8410	1			T1	16		T2	18		T3	8
valid_sources[0x35]	6882	1			T1	5		T2	18		T3	8
valid_sources[0x36]	7601	1			T1	9		T2	30		T3	10
valid_sources[0x37]	8508	1			T1	3		T2	26		T3	9
valid_sources[0x38]	11387	1			T1	5		T2	48		T3	7
valid_sources[0x39]	7738	1			T1	3		T2	22		T3	11
valid_sources[0x3a]	8735	1			T1	17		T2	16		T3	15
valid_sources[0x3b]	7293	1			T1	14		T2	23		T3	7
valid_sources[0x3c]	11232	1			T1	7		T2	33		T3	10
valid_sources[0x3d]	11577	1			T1	15		T2	27		T3	1
valid_sources[0x3e]	7573	1			T1	7		T2	37		T3	10
valid_sources[0x3f]	13975	1			T1	11		T2	14		T3	1
valid_sources[0x40]	11099	1			T1	5		T2	24		T3	8
valid_sources[0x41]	7649	1			T1	19		T2	27		T3	8
valid_sources[0x42]	8165	1			T1	12		T2	53		T3	10
valid_sources[0x43]	7358	1			T1	8		T2	39		T3	15
valid_sources[0x44]	15384	1			T1	5		T2	22		T3	8
valid_sources[0x45]	8953	1			T1	4		T2	24		T3	6
valid_sources[0x46]	9908	1			T1	2		T2	35		T3	12
valid_sources[0x47]	6896	1			T1	18		T2	20		T3	10
valid_sources[0x48]	7230	1			T1	10		T2	31		T3	11
valid_sources[0x49]	9674	1			T1	6		T2	36		T5	4
valid_sources[0x4a]	9883	1			T1	7		T2	31		T3	11
valid_sources[0x4b]	10077	1			T1	10		T2	5		T3	13
valid_sources[0x4c]	14072	1			T1	7		T2	22		T3	7
valid_sources[0x4d]	7153	1			T1	5		T2	24		T3	16
valid_sources[0x4e]	7377	1			T1	16		T2	67		T3	21
valid_sources[0x4f]	8735	1			T1	17		T2	41		T3	16
valid_sources[0x50]	7264	1			T1	6		T2	36		T3	19
valid_sources[0x51]	9497	1			T1	9		T2	39		T3	10
valid_sources[0x52]	7372	1			T1	6		T2	25		T3	16
valid_sources[0x53]	7560	1			T1	7		T2	35		T3	6
valid_sources[0x54]	11836	1			T1	14		T2	40		T3	19
valid_sources[0x55]	7134	1			T1	6		T2	63		T5	5
valid_sources[0x56]	8274	1			T1	11		T2	24		T3	7
valid_sources[0x57]	10114	1			T1	12		T2	14		T3	8
valid_sources[0x58]	12496	1			T1	4		T2	21		T3	13
valid_sources[0x59]	11239	1			T1	27		T2	46		T3	9
valid_sources[0x5a]	6973	1			T1	35		T2	26		T3	3
valid_sources[0x5b]	11711	1			T1	10		T2	33		T3	1
valid_sources[0x5c]	6989	1			T1	10		T2	33		T3	7
valid_sources[0x5d]	6970	1			T1	11		T2	14		T3	16
valid_sources[0x5e]	7049	1			T1	15		T2	23		T5	5
valid_sources[0x5f]	9958	1			T1	19		T2	4		T3	11
valid_sources[0x60]	6882	1			T1	1		T2	16		T3	28
valid_sources[0x61]	9947	1			T1	19		T2	52		T3	10
valid_sources[0x62]	33911	1			T1	12		T2	29		T3	3
valid_sources[0x63]	6728	1			T1	8		T2	25		T3	3
valid_sources[0x64]	6536	1			T1	6		T2	53		T3	10
valid_sources[0x65]	7256	1			T1	12		T2	29		T3	10
valid_sources[0x66]	7423	1			T1	3		T2	25		T3	14
valid_sources[0x67]	7111	1			T1	5		T2	60		T3	14
valid_sources[0x68]	15065	1			T1	18		T2	28		T3	25
valid_sources[0x69]	6994	1			T1	5		T2	15		T3	8
valid_sources[0x6a]	7045	1			T1	1		T2	48		T3	2
valid_sources[0x6b]	7202	1			T1	12		T2	23		T3	3
valid_sources[0x6c]	7118	1			T1	18		T2	11		T3	13
valid_sources[0x6d]	10819	1			T1	5		T2	57		T3	5
valid_sources[0x6e]	11558	1			T1	10		T2	66		T3	26
valid_sources[0x6f]	11724	1			T1	5		T2	61		T3	1
valid_sources[0x70]	7489	1			T1	5		T2	20		T3	13
valid_sources[0x71]	13628	1			T1	9		T2	42		T3	9
valid_sources[0x72]	8250	1			T1	10		T2	39		T3	5
valid_sources[0x73]	10106	1			T1	12		T2	27		T3	21
valid_sources[0x74]	6881	1			T1	31		T2	62		T3	17
valid_sources[0x75]	8218	1			T1	15		T2	11		T3	11
valid_sources[0x76]	14929	1			T1	9		T2	36		T3	8
valid_sources[0x77]	7421	1			T1	11		T2	66		T3	2
valid_sources[0x78]	11385	1			T1	11		T2	30		T3	24
valid_sources[0x79]	11292	1			T1	7		T2	82		T3	11
valid_sources[0x7a]	8221	1			T1	7		T2	49		T3	9
valid_sources[0x7b]	7471	1			T1	7		T2	34		T3	13
valid_sources[0x7c]	8137	1			T1	5		T2	40		T3	12
valid_sources[0x7d]	7159	1			T1	13		T2	18		T3	14
valid_sources[0x7e]	15732	1			T1	40		T2	44		T3	4
valid_sources[0x7f]	6988	1			T1	18		T2	26		T3	13
valid_sources[0x80]	7128	1			T1	13		T2	26		T3	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1080105

1

T1

1226

T2

6054

T3

1290

values[0x0]

all_enables

biggest_size

80169

1

T1

71

T2

182

T3

88

values[0x1]

all_enables

biggest_size

57664

1

T1

60

T2

120

T3

59