Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28251	1			T1	23		T2	24		T3	26
auto[PWRUP]	101	1			T6	1		T21	1		T24	2
auto[ONEST_0]	63	1			T24	3		T28	2		T40	2
auto[ONEST_021]	13	1			T6	2		T28	1		T181	1
auto[ONEST_1]	69	1			T21	1		T24	3		T39	2
auto[ONEST_DONE]	2	1			T189	1		T190	1		-	-
auto[LP_0]	113	1			T6	2		T24	1		T28	2
auto[LP_021]	21	1			T6	3		T28	1		T191	1
auto[LP_1]	127	1			T6	2		T24	1		T40	1
auto[LP_EVAL]	54	1			T6	1		T39	1		T35	2
auto[LP_SLP]	455	1			T6	4		T24	7		T28	8
auto[LP_PWRUP]	23	1			T39	1		T192	1		T35	1
auto[NP_0]	147	1			T6	1		T24	3		T39	1
auto[NP_021]	27	1			T193	2		T191	1		T181	1
auto[NP_1]	151	1			T6	1		T24	2		T28	1
auto[NP_EVAL]	37	1			T6	2		T11	1		T21	1
auto[NP_DONE]	1	1			T194	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T39

1

T195

1

T196

1

min

27773

1

T1

23

T2

24

T3

26

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27781	1			T1	23		T2	24		T3	26
pow[0x1]	11	1			T39	1		T184	1		T195	1
pow[0x2]	14	1			T197	1		T196	2		T198	1
pow[0x3]	35	1			T6	2		T40	1		T193	1
pow[0x4]	54	1			T21	1		T24	2		T39	1
pow[0x5]	98	1			T6	4		T11	1		T21	1
pow[0x6]	202	1			T6	4		T11	1		T24	3
pow[0x7]	472	1			T6	5		T21	1		T24	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

180

1

T6

3

T24

2

T28

3

min

27356

1

T1

23

T2

24

T3

26

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27356	1			T1	23		T2	24		T3	26
pow[0x4]	2	1			T193	1		T199	1		-	-
pow[0x6]	2	1			T106	1		T200	1		-	-
pow[0x7]	1	1			T201	1		-	-		-	-
pow[0x8]	4	1			T28	1		T78	1		T202	2
pow[0x9]	6	1			T28	2		T203	1		T17	2
pow[0xa]	17	1			T39	2		T191	1		T73	2
pow[0xb]	33	1			T39	1		T193	1		T36	1
pow[0xc]	63	1			T6	1		T24	1		T40	1
pow[0xd]	121	1			T6	3		T24	2		T28	1
pow[0xe]	252	1			T6	6		T21	1		T24	6
pow[0xf]	532	1			T6	2		T11	1		T21	1