Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2264	1			T6	18		T11	8		T12	7
auto[PWRUP]	133	1			T6	1		T11	2		T21	3
auto[ONEST_0]	67	1			T21	1		T24	1		T39	1
auto[ONEST_021]	13	1			T40	1		T191	1		T184	1
auto[ONEST_1]	80	1			T39	2		T193	2		T13	1
auto[ONEST_DONE]	4	1			T24	1		T326	1		T195	1
auto[LP_0]	132	1			T6	2		T21	1		T24	3
auto[LP_021]	33	1			T6	1		T24	1		T39	1
auto[LP_1]	137	1			T6	2		T21	1		T24	1
auto[LP_EVAL]	50	1			T24	1		T39	1		T193	1
auto[LP_SLP]	523	1			T6	5		T12	2		T21	1
auto[LP_PWRUP]	34	1			T24	1		T39	1		T40	1
auto[NP_0]	205	1			T6	4		T11	1		T12	1
auto[NP_021]	49	1			T11	1		T24	2		T39	1
auto[NP_1]	233	1			T6	3		T12	2		T21	5
auto[NP_EVAL]	39	1			T24	3		T39	1		T192	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T73

1

T106

1

T327

2

min

1987

1

T6

8

T11

9

T12

11

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1999	1			T6	8		T11	9		T12	11
pow[0x1]	14	1			T6	1		T28	1		T13	1
pow[0x2]	17	1			T40	1		T191	1		T328	1
pow[0x3]	32	1			T39	1		T35	3		T191	2
pow[0x4]	56	1			T6	1		T12	1		T21	2
pow[0x5]	113	1			T6	4		T24	2		T39	1
pow[0x6]	250	1			T6	6		T11	1		T21	2
pow[0x7]	516	1			T6	9		T21	1		T24	11

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

220

1

T6

2

T11

1

T21

1

min

1394

1

T11

9

T12

9

T21

11

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1399	1			T11	9		T12	9		T21	11
pow[0x1]	2	1			T216	1		T194	1		-	-
pow[0x2]	33	1			T35	2		T36	1		T37	3
pow[0x3]	52	1			T11	1		T12	3		T21	4
pow[0x4]	51	1			T34	2		T13	1		T35	4
pow[0x5]	2	1			T327	1		T329	1		-	-
pow[0x6]	1	1			T92	1		-	-		-	-
pow[0x7]	1	1			T195	1		-	-		-	-
pow[0x8]	6	1			T28	1		T40	1		T330	1
pow[0x9]	10	1			T21	1		T28	1		T40	1
pow[0xa]	15	1			T28	1		T39	1		T40	1
pow[0xb]	39	1			T24	1		T39	1		T193	1
pow[0xc]	89	1			T6	1		T24	2		T28	3
pow[0xd]	128	1			T6	2		T24	2		T28	3
pow[0xe]	288	1			T6	5		T21	4		T24	3
pow[0xf]	574	1			T6	12		T11	1		T21	1